为什么Spartan 6 JTAG发生故障但SPI存储器可以编程？

您能否在闪存上执行验证操作？在jtag模式或spi模式下配置失败后也可以读取fpga的状态寄存器并发布。
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以下为原文

Can you please perform verify operation on flash?

Also read the status register of the fpga after configuration failure either in jtag mode or in spi mode and post it.

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验证输出：
信息：iMPACT  - 当前时间：2014年2月20日2:30:39 PMPROGRESS_START  - 启动操作。此设备链的最大TCK工作频率：25000000.Validating chain ...边界扫描链成功验证。'1'：SPI
未检测到访问核心。
SPI访问核心将被下载到设备以启用operations：iMPACT  - 下载核心文件C：/Xilinx/14.5/ISE_DS/ISE/spartan6/data/xc6slx16_spi.cor.'1'：下载核心...... LCK_cycle =
NoWait.LCK周期：NoWaitdone.'1'：读取状态寄存器内容... INFO：iMPACT：2219  - 状态寄存器值：INFO：iMPACT  -  0011 1100 1110 1100 INFO：iMPACT：2492  - '1'：已完成下载核心到
device.INFO:iMPACT  - 地址0x00000000在页面0.INFO:iMPACT  - 地址0x0007176F在页面880.'1'：验证设备... done.'1'：验证成功完成.INFO:iMPACT - '1'
：检查完成的针......完成。'1'：编程终止。
DONE没有变高.PROGRESS_END  - 结束操作。经过的时间= 156秒。
FPGA JTAG编程后的控制台输出：
信息：iMPACT  - 当前时间：2/20/2014 2:34:29 PMPROGRESS_START  - 启动操作。此设备链的最大TCK工作频率：25000000.Validating chain ...边界扫描链验证成功。'1'：编程
设备... LCK_cycle = NoWait.LCK周期：NoWaitdone .'1'：读取状态寄存器内容... [0]
CRC错误：0 [1] IDCODE错误：0 [2] DCM锁定状态：0 [3] GTS_CFG_B状态：0 [4] GWE状态：0 [5] GHIGH状态：0 [6]解密错误：0 [7]
DECRYPTOR ENABLE：0 [8] HSWAPEN PIN：0 [9] MODE PIN M [0]：0 [10] MODE PIN M [1]：0 [11]保留：0 [12] INIT_B PIN：0 [13] DONE
PIN：0 [14] SUSPEND STATUS：0 [15] FALLBACK STATUS：0INFO：iMPACT：2219  - 状态寄存器值：INFO：iMPACT  -  0000 0000 0000 0000 INFO：iMPACT：579  - '1'：完成将位文件下载到设备
.INFO：iMPACT：188  - '1'：编程成功完成。
LCK_cycle = NoWait.LCK周期：NoWaitINFO：iMPACT  - '1'：检查完成的引脚.... done.'1'：编程终止。
DONE没有变高.PROGRESS_END  - 结束操作。经过的时间= 10秒。
状态寄存器输出：
信息：iMPACT  - 当前时间：2014/2/20 2:35:55 PM此设备链的最大TCK工作频率：25000000.Validating chain ...边界扫描链成功验证。'1'：读取引导寄存器内容..
。[0]
VALID_0  - 错误或启动结束（EOS）检测：0 [1] FALLBACK_0  - 检测到FALLBACK重新配置检测：0 [2]保留：0 [3] WTO_ERROR_0  - 看门狗超时错误：0 [4] ID_ERROR_0  -  FPGA器件IDCODE错误
：0 [5] CRC_ERROR_0  - 循环冗余校验（CRC）错误：0 [6] VALID_1  - 错误或启动结束（EOS）检测到：0 [7] FALLBACK_1  -  FALLBACK RECONFIGURATION ATTEMT检测到：0 [8]保留：0 [
9] WTO_ERROR_1  - 看门狗超时错误：0 [10] ID_ERROR_1  -  FPGA器件IDCODE错误：0 [11] CRC_ERROR_1  - 循环冗余校验（CRC）错误：0 [12]罢工CNT  - 罢工计数用于反击尝试：0 [13]
] STRIKE_CNT  - 反击命令的罢工数：0 [14] STRIKE_CNT  - 反击击败的罢工数：0 [15] STRIKE_CNT  - 反击命令的罢工数：0'1'：读取状态寄存器内容...... [0]
CRC错误：0 [1] IDCODE错误：0 [2] DCM锁定状态：1 [3] GTS_CFG_B状态：0 [4] GWE状态：0 [5] GHIGH状态：0 [6]解密错误：0 [7]
DECRYPTOR ENABLE：0 [8] HSWAPEN PIN：0 [9] MODE PIN M [0]：1 [10] MODE PIN M [1]：0 [11]保留：0 [12] INIT_B PIN：1 [13] DONE
PIN：0 [14] SUSPEND STATUS：0 [15] FALLBACK STATUS：0



以下为原文

Verify Output:
INFO:iMPACT - Current time: 2/20/2014 2:30:39 PM
PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 25000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': SPI access core not detected. SPI access core will be downloaded to the device to enable operations.
INFO:iMPACT - Downloading core file C:/Xilinx/14.5/ISE_DS/ISE/spartan6/data/xc6slx16_spi.cor.
'1': Downloading core...
LCK_cycle = NoWait.
LCK cycle: NoWait
done.
'1': Reading status register contents...
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 1100 1110 1100
INFO:iMPACT:2492 - '1': Completed downloading core to device.
INFO:iMPACT - Address 0x00000000 is in page 0.
INFO:iMPACT - Address 0x0007176F is in page 880.
'1': Verifying device...done.
'1': Verification completed successfully.
INFO:iMPACT - '1': Checking done pin....done.
'1': Programming terminated. DONE did not go high.
PROGRESS_END - End Operation.
Elapsed time = 156 sec.
 
Console output after JTAG programming of FPGA:
INFO:iMPACT - Current time: 2/20/2014 2:34:29 PM
PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 25000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': Programming device...
LCK_cycle = NoWait.
LCK cycle: NoWait
done.
'1': Reading status register contents...
[0] CRC ERROR : 0
[1] IDCODE ERROR : 0
[2] DCM LOCK STATUS : 0
[3] GTS_CFG_B STATUS : 0
[4] GWE STATUS : 0
[5] GHIGH STATUS : 0
[6] DECRYPTION ERROR : 0
[7] DECRYPTOR ENABLE : 0
[8] HSWAPEN PIN : 0
[9] MODE PIN M[0] : 0
[10] MODE PIN M[1] : 0
[11] RESERVED : 0
[12] INIT_B PIN : 0
[13] DONE PIN : 0
[14] SUSPEND STATUS : 0
[15] FALLBACK STATUS : 0
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0000 0000 0000 0000
INFO:iMPACT:579 - '1': Completed downloading bit file to device.
INFO:iMPACT:188 - '1': Programming completed successfully.
LCK_cycle = NoWait.
LCK cycle: NoWait
INFO:iMPACT - '1': Checking done pin....done.
'1': Programming terminated. DONE did not go high.
PROGRESS_END - End Operation.
Elapsed time = 10 sec.
 
Status register output:
INFO:iMPACT - Current time: 2/20/2014 2:35:55 PM
Maximum TCK operating frequency for this device chain: 25000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': Reading bootsts register contents...
[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED : 0
[1] FALLBACK_0 - FALLBACK RECONFIGURATION ATTEMPT DETECTED : 0
[2] RESERVED : 0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR : 0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR : 0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[6] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED : 0
[7] FALLBACK_1 - FALLBACK RECONFIGURATION ATTEMPT DETECTED : 0
[8] RESERVED : 0
[9] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR : 0
[10] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR : 0
[11] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[12] STRIKE CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[13] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[14] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[15] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
'1': Reading status register contents...
[0] CRC ERROR : 0
[1] IDCODE ERROR : 0
[2] DCM LOCK STATUS : 1
[3] GTS_CFG_B STATUS : 0
[4] GWE STATUS : 0
[5] GHIGH STATUS : 0
[6] DECRYPTION ERROR : 0
[7] DECRYPTOR ENABLE : 0
[8] HSWAPEN PIN : 0
[9] MODE PIN M[0] : 1
[10] MODE PIN M[1] : 0
[11] RESERVED : 0
[12] INIT_B PIN : 1
[13] DONE PIN : 0
[14] SUSPEND STATUS : 0
[15] FALLBACK STATUS : 0

由于FPGA配置了.cor文件，我不怀疑这是一个FPGA问题。即使闪存编程成功。你可以尝试另一个位文件，看看是否编程？
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以下为原文

Since the FPGA was getting configured with the .cor file, I don't suspect this to be a FPGA issue.

Even the flash is programmed successfully.

Can you try another bit file as see if that gets programmed?-----------------------------------------------------------------------------------------------
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

Give Kudos to a post which you think is helpful.

我会尝试的。
这需要一点时间。
我会发布结果。谢谢



以下为原文

I will try that. It will take a little while. I will post the results.

Thanks

您是否有可以监视INIT_B引脚的示波器？
尝试JTAG加载比特流后的状态看起来可能与开机后期望的状态相似。
这可能表示电源故障，可能是由于设计启动时的突然动态负载。
如果是这种情况，您可能会在编程尝试结束时在iNIT_B行上看到另一个脉冲。
-  Gabor



以下为原文

Do you have a scope you can monitor the INIT_B pin with?  The status after attempting JTAG load of your bitstream looks suspicously like the state you'd expect after power-on.  This might indicate a power supply failure, possibly due to the sudden dynamic load when the design starts up.  If that's the case you might see another pulse on the iNIT_B line at the end of the programming attempt.
-- Gabor