[问答]

有办法让JTAG直接将一个文件下载到Spartan 3E芯片而无需编写附加的闪存吗

问答对人有帮助，内容完整，我也想知道答案 0 我想知道有没有办法让JTAG直接将一个文件（或其他文件类型）下载到Spartan 3E芯片而无需编写附加的闪存。这样在执行程序构建和测试时，每次都会绕过FLASH编程。这节省了FLASH的时间和磨损。我使用Digilentinc USB JTAG编程器（和ADEPT）在Spartan 6上使用了这种方法并取得了相当的成功。 Spartan 3E似乎接受了该文件，但它没有运行。带有3E的开发板在JTAG链中有一个FLASH存储器芯片（XF02）。如果程序员指向FLASH，它会擦除，编程，验证，并且FPGA按预期运行。关于如何做到这一点的任何想法？比尔，谢谢以上来自于谷歌翻译以下为原文 I was wondering is there is a way to JTAG download a bit file (or other file type) directly to the Spartan 3E chip without programming the attached flash memory. This would bypass programming the FLASH each time while doing program construction and testing. This saves time, and wear and tear on the FLASH. I have used this method on the Spartan 6 using the Digilentinc USB JTAG programmer (and ADEPT) with reasonable success. The Spartan 3E seems to accept the file, but it does not run. The development board with the 3E has a FLASH memory chip (XF02) in the JTAG chain. If the programmer is pointed to the FLASH, it does erase, program, verify, and the FPGA runs as expected. Any Ideas on how to do this? Thanks, Bill 0
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答案对人有帮助，有参考价值 0 wvancura写道：我想知道有没有办法让JTAG直接将一个文件（或其他文件类型）下载到Spartan 3E芯片而无需编写附加的闪存。这样在执行程序构建和测试时，每次都会绕过FLASH编程。这节省了FLASH的时间和磨损。我使用Digilentinc USB JTAG编程器（和ADEPT）在Spartan 6上使用了这种方法并取得了相当的成功。 Spartan 3E似乎接受了该文件，但它没有运行。带有3E的开发板在JTAG链中有一个FLASH存储器芯片（XF02）。如果程序员指向FLASH，它会擦除，编程，验证，并且FPGA按预期运行。关于如何做到这一点的任何想法？比尔，谢谢通过JTAG直接下载到FPGA已成为Xilinx多年来的一项功能。我一直这样做。当然，问题在于下载后无法循环供电。配置完成后，FPGA将以通常的方式初始化。 ----------------------------是的，我这样做是为了谋生。以上来自于谷歌翻译以下为原文 wvancura wrote: I was wondering is there is a way to JTAG download a bit file (or other file type) directly to the Spartan 3E chip without programming the attached flash memory. This would bypass programming the FLASH each time while doing program construction and testing. This saves time, and wear and tear on the FLASH. I have used this method on the Spartan 6 using the Digilentinc USB JTAG programmer (and ADEPT) with reasonable success. The Spartan 3E seems to accept the file, but it does not run. The development board with the 3E has a FLASH memory chip (XF02) in the JTAG chain. If the programmer is pointed to the FLASH, it does erase, program, verify, and the FPGA runs as expected. Any Ideas on how to do this? Thanks, Bill Download directly to the FPGA via JTAG has been a feature available from Xilinx for many years. I do it all the time. The gotcha, of course, is that you cannot cycle power after the download. Once configuration is complete, the FPGA initializes in its usual way. ----------------------------Yes, I do this for a living.

2019-6-14 10:43:46 评论举报黄淳