如何解决使用时钟向导的时钟稳定性问题？

你好，
当我使用时钟向导生成不同的时钟时，我生成的时钟频率不稳定，它们会偏离频率。
我正在尝试生成曼彻斯特编码信号并在另一个spartan6上解码它。
问题是输出信号（曼彻斯特信号）并不总是遵循完全相同的频率，因此它不能被正确解码，因为它不是接收器所规定的频率。
有什么想法如何解决问题？
谢谢你们。



以下为原文

Hello,
 
When I generate different clocks with the clocking wizard, the clocks I generate are not stable in frequency and they diverts from what would be the frequency.
 
I am trying to generate a Manchester coded signal and decode it on another spartan6. The problem is that the output signal (Manchester signal) not always follows exactly the same frequency so it cannot be decoded propperly because it is not of the frequency the receiver spects.
 
Any idea of how to solve the problem?
 
Thank you all.

一世，
我建议您的100 MHz存在严重问题....
垃圾输入=垃圾输出。
如果一个简单的计数器没有更好的工作，那么100 MHz就会出现问题，或者测量方式出现问题。
简化，直到你得到一个理智和理性的结果！
Austin Lesea主要工程师Xilinx San Jose
在原帖中查看解决方案



以下为原文

i,
 
I suggest there is something seriously wrong with your 100 MHz....
 
Garbage in = garbage out.
 
If a simple counter works no better, then either there is something very wrong with the 100 MHz, or something very wrong with the way you are measuring.  Simplify until you get a sane and rational result!
 
 
Austin Lesea
Principal Engineer
Xilinx San JoseView solution in original post

一世，
问题是什么？
不是一个稳定的时钟可能意味着什么。
抖动太多了？
频率错误？
时钟停止？
Austin Lesea主要工程师Xilinx San Jose



以下为原文

i,
 
What is the problem?  Not a stable clock could mean practically anything.

Too much jitter?
 
Wrong frequency?
 
Clock stops?
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

你好，
问题是输出频率连续变化。
一旦我开始监测它，假设频率的值为6.25 MHz，从6.13变为6.37 MHz。
根据时钟向导估计，抖动可能约为320 ps，这意味着6.24至6.26 MHz的变化。
我使用时钟向导3.3提供的块，100 MHz输入，用于生成100,12.5和6.25 MHz。
我使用的是ISE 13.4。
设计目标：时间表现。
下面我附上了ucf文件
--------------------------------------------------
--------------------------------------------------
----------
净clk_input LOC = C10;
＃100 MHz #Net clk_input LOC = V10;
＃40 MHzNet rst LOC = A4;
＃rst，sw 4Net PPCmode LOC = B3;
＃mode，sw 1Net start_global LOC = V4;
#button #Connectoror J5Net data_out LOC = F15;
#pin 1 del J5Net data_out LOC = F16;
#pin 2 del J5Net data_out LOC = C17;
#pin 3 del J5Net data_out LOC = C18;
#pin 4 del J5Net data_out LOC = F14;
#pin 7 del J5Net data_out LOC = G14;
#pin 8 del J5Net data_out LOC = D17;
#pin 9 del J5Net data_out LOC = D18;
#pin 10 del J5 #CONNECTOR J4Net serialdata LOC = H12;
#pin 1 del J4Net manch LOC = G13;
#pin 2 del J4Net clk1x LOC = E16;
#pin 3 del J4Net filtrada LOC = E18;
#pin 4 del J4Net serial_data LOC = K12;
#pin 7 del J4Net loadDPM1 LOC = K13;
#pin 8 del J4
净clk16x CLOCK_DEDICATED_ROUTE = TRUE;净CLK CLOCK_DEDICATED_ROUTE = TRUE;净CLK2X CLOCK_DEDICATED_ROUTE = TRUE;净clk_input CLOCK_DEDICATED_ROUTE = TRUE;
--------------------------------------------------
--------------------------------------------------
----------
如果您需要更多信息，我可以附上完整的设计。
感谢您的时间。
干杯。



以下为原文

Hello,
 
the problem is that the output frequency changes continuously. Once I start monitoring it, the value of the frequency of wich is supposed to be 6.25 MHz changes from 6.13 to 6.37 MHz. According to clocking wizard estimation jitter might be about 320 ps, wich would mean 6.24 to 6.26 MHz variation.
 
I am using a block provided by clocking wizard 3.3 with 100 MHz input for generating 100, 12.5 and 6.25 MHz. I am using ISE 13.4. Desing Goal: Timing Performance.
 
Below I attached the ucf file
 
--------------------------------------------------------------------------------------------------------------
 
Net clk_input LOC=C10;                # 100 MHz
#Net clk_input LOC=V10;               # 40 MHz
Net rst LOC=A4;                               # rst, sw 4
Net PPCmode LOC=B3;                # mode, sw 1
Net start_global LOC=V4;              # button

#CONNECTOR J5
Net data_out<0> LOC=F15;                    # pin 1 del J5
Net data_out<1> LOC=F16;                    # pin 2 del J5
Net data_out<2> LOC=C17;                    # pin 3 del J5
Net data_out<3> LOC=C18;                    # pin 4 del J5

Net data_out<4> LOC=F14;                    # pin 7 del J5
Net data_out<5> LOC=G14;                    # pin 8 del J5
Net data_out<6> LOC=D17;                    # pin 9 del J5
Net data_out<7> LOC=D18;                    # pin 10 del J5
                                           
#CONNECTOR J4
Net serialdata LOC=H12;                        # pin 1 del J4
Net manch LOC=G13;                            # pin 2 del J4
Net clk1x LOC=E16;                               # pin 3 del J4
Net filtrada LOC=E18;                            # pin 4 del J4
Net serial_data LOC=K12;                    # pin 7 del J4
Net loadDPM1 LOC=K13;                      # pin 8 del J4
 
Net clk16x CLOCK_DEDICATED_ROUTE = TRUE;
Net clk CLOCK_DEDICATED_ROUTE = TRUE;
Net clk2x CLOCK_DEDICATED_ROUTE = TRUE;
Net clk_input CLOCK_DEDICATED_ROUTE = TRUE;
 
--------------------------------------------------------------------------------------------------------------
 
If you need further information I can attach the complete design.
 
Thank you for your time.
 
Cheers.

你是如何测量输出频率的？
你在看曼彻斯特的实际编码吗？
信号，或从同一时钟产生的简单方波？
-  Gabor



以下为原文

How are you measuring the output frequency?  Are you looking at the actual Manchester encoded
signal, or a simple square wave generated from the same clock?
-- Gabor

两个都。
我正在测量我要发送的实际曼彻斯特编码信号以及生成的时钟。
在这两个信号中，我发现了这些差异
我知道通过引脚获取clk信号不是一个好的设计实践，但它是我在示波器中测量生成的clk方波频率的唯一方法。



以下为原文

Both of them.
 
I am measuring the actual Manchester encoded signal I want to send and the generated clock as well. In both signals I detect those differences.
 
I know that getting a clk signal through a pin is not a good design practice but it is the only way I found for measuring the generated clk square wave frequency in my oscilloscope.

如果您使用示波器测量频率，您应该知道它们
这些测量不是很好，因为它们依赖于测量时钟周期
和反转。
时钟周期测量受采样分辨率的限制
以及准确触发的能力。
信号边缘上的任何噪声都会有所贡献
测量误差。
使用示波器可以做到的最好
启用重复计时并使用过滤。
即便如此，我也不确定你会得到一个
真实的频率变化指示。
-  Gabor



以下为原文

If you're using an oscilloscope to measure the frequency, you should know that they
are not very good at such measurements, as they rely on measuring the clock period
and inverting.  The clock period measurement is limited by the sampling resolution
and the ability to accurately trigger.  Any noise on the signal edge will contribute
error to the measurement.  The best you can do with an oscilloscope would be
to enable repetetive timing and use filtering.  Even then, I'm not sure you'd get a
true indication of the actual frequency variation.
-- Gabor

感谢你的信息。
问题是它是安捷伦混合信号示波器，每秒20 GSamples，因此测量足够可靠。
在任何情况下，我通过反转我自己测量的周期来手动测量它。
此外，其他信号的频率是正确的。
此外，当我在Virtex-5 ml507电路板上加载相同的设计（几乎没有变化）时，问题就消失了，信号示波器的测量结果还可以。
知道为什么会这样吗？
先谢谢你。



以下为原文

Thanks for your information.
 
The thing is that it is an Agilent Mixed Signal Oscilloscope with 20 GSamples per second so the measurement is reliable enough. In any case, I am measuring it manualy by inverting the period measured by myself. In addition, other signals' frequencies are correct.
 
Besides, when I load this same design (with little changes) on a Virtex-5 ml507 board the problem disappears and the measurements with the signal oscilloscope are ok.
 
Any idea of why can it be?
 
Thank you in advance.

在尝试调试之前，我会检查100 MHz时钟以确保它是稳定的
其他事情。
您确定DCM或PLL实际上已锁定吗？
如果你是
使用PLL，你检查过你的VccAux没有噪音吗？
-  Gabor



以下为原文

I would check the 100 MHz clock to make sure it is stable before you try to debug
other things.  Have you determined that the DCM or PLL is actually locked?  If you're
using a PLL, have you checked that your VccAux is not noisy?
-- Gabor

的Gabor，
我怀疑他的范围是如此聪明，以至于它自成一体。
他可能想要做一些故障排除，因为你需要：
1.其他时钟频率是什么样的？
2. DCM已锁定吗？
等等
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Gabor,

I suspect his scope is so smart, that it sets itself.  He may want to do some troubleshooting as you suggust:
 
1.  What do other clock frequencies look like?
 
2.  Is the DCM locked?
 
etc.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

一世，
你有没有测量时钟，并且在示波器上同时输出时钟？
如果它有两个探针 - 使用它们。
输出时钟（如果触发它）将同步输入时钟（边缘应对齐+/- 100ps）。
如果你有一个tghird探针，montor LOCKED。
另外，CLK_STOPPED状态引脚怎么样？
它在做什么？
不确定如何从相同的DCM获得12.5 MHz和6.25 MHz（它只有一个CLK_DV输出。似乎需要两个DCM，两个都由100 MHz驱动，一个用于/ 8，另一个用于/
16。
使用12.5 MHz作为触发器，您应该能够找到什么是周期滑动（丢失或获得时钟）。
如果您看到周期滑动，那么请查看时钟输入引脚上的信号完整性 - 您可能会出现边缘较差，从而导致创建/丢弃时钟的毛刺。
如果是这种情况，那么LOCKED应该迷路（去假）。
你一直在监视LOCKED吗？
Austin Lesea主要工程师Xilinx San Jose



以下为原文

i,
 
Have you measured the clock in, and the clock out at the same time on the scope?  If it has two probes -- USE THEM.
 
The output clock (if you trigger on it) will sync the input clock (the edges should be aligned +/- 100ps).  If you have a tghird probe, montor LOCKED.  Also, what about the CLK_STOPPED status pin?  What is it doing?

Not sure how you get both 12.5 MHz, and 6.25 MHz from the same DCM (it has only one CLK_DV output.  Seems like that takes two DCM's, both driven by 100 MHz, one to do the /8, the other to do the /16.
 
Using the 12.5 MHz as the trigger, you should be able to find what is cycle slipping (losing or gaining clocks).  If you see cycle slipping, then look at the signal integrity on the clock input pin(s) -- you may have poor edges causing glitches which create/drop clocks.  If that is the case, then LOCKED should be getting lost (go false).  Are you continuously monitoring LOCKED?
 
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

你好奥斯汀，
我已经检查了你在最新帖子中的建议：附上你会发现100 MHz输入和所有输出包括锁定信号的范围捕获。
锁定信号为“1”且不会降至“0”。
100 MHz输出和输入不同步+/- 100 ps。
我还附上了时钟向导的捕获信息，因为你告诉我不确定如何获得12.5和6.25 MHz信号。
请注意，我使用的是时钟向导3.3提供的块，而且我没有改变很多东西的可能性。
例如，该内核不提供CLK_DV预固定输出（与之前版本中使用的DCM内核（如Virtex5）一样）。
CLK_STOPED信号既不出现在此时钟向导的可选选项中。
亲切的问候。
scope_capture_and_clocking_wizard.pdf 110 KB



以下为原文

Hello Austin,
 
I've checked what you suggested in your latest post: attached you will find a capture of the scope with the 100 MHz input and all outputs including locked signal. Locked signal is '1' and does not fall to '0'. 100 MHz output and input are not synchronised +/- 100 ps.
 
I've attached as well a capture of the clocking wizard as you told me that not sure how I get both 12.5 and 6.25 MHz signals. Note that I am using a block provided by clocking wizard 3.3 and I have not the cappability to change many things. For example, this core does not provide the CLK_DV pre-fixed output (as with DCM cores used in previous versions such as Virtex5). The CLK_STOPED signal neither does appear among the selectable options of this clocking wizard.
 
Kind regards.
            scope_capture_and_clocking_wizard.pdf ‏110 KB

从核心生成器的屏幕截图来看，我会说你使用的是PLL而不是
一个DCM来创建你的时钟。
如果是这种情况，您确实需要使用VccAux引脚
确保你有一个干净的供应。
VccAux的变化会导致PLL的波动
VCO频率，导致你所看到的那种频率调制。
-  Gabor



以下为原文

Judging from the screen shot from the Core Generator, I'd say that you are using a PLL and not
a DCM to create your clocks.  If this is the case, you really need to scope on the VccAux pins
to make sure you have a clean supply.  Variations in VccAux can cause fluctuations in the PLL's
VCO frequency, causing the sort of frequency modulation you're seeing.
-- Gabor

Ĵ，
您可能需要手动实例化它，而不是使用向导，因为您需要_ADV原语来访问您可能需要的所有信号。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

j,
 
You may have to instantiate it by hand, rather than use the wizard, as you will need the _ADV primitive to gain access to all the signals you may need.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

的Gabor，
我尝试使用DCM_SP和PLL_BASE。
我现在使用的是原始DCM_CLKGEN。
在不是一种情况下，频率是完全正确的：抖动保持如此重要。
我也尝试组合生成时钟信号（知道这不是一个好的设计实践），并且结果与其他情况一样糟糕或最差。
从100 MHz产生有效的6.25 MHz是如此困难吗？
从理论上讲，应该使用16分频器操作。
我尝试将电源从USB更改为微型USB，并且没有发生实质性变化。
我不太了解VccAux引脚是什么，或者至少我找不到它们。
考虑到FPGA集成到电路板（lx9）中，并且用户不必关心电气连接。
最好的祝福。



以下为原文

Gabor,
 
I tried using DCM_SP and PLL_BASE. I am now using Primitive DCM_CLKGEN. In not a single case the frequency is completely correct: the jitter keeps being so much significant. I have also tried generating the clock signals combinationaly (knowing that is not a good design practice) and the resuls are as bad or worst than in the other cases.
 
Is it so difficult to generate valid 6.25 MHz from 100 MHz?? In theory, that should be by using a 16 divider operation.
 
I tried as well changing the power supply from USB to micro USB and no substantial change happened. I don not understand very well what are the VccAux pins, or at least I cannot find them. Take into account that the FPGA comes integrated into the board (lx9) and the user is suppsed to not care about the electrical connections.
 
Best regards.

奥斯汀，
我不明白你用“手动实例化”的意思。
如果您能给我一些进一步的信息或者给我一个例子，我将不胜感激。
更改为DCM_CLKGEN我得到CLK_STOPPED信号，仅当LOCKED ='1'且CLK_STOPPED ='0'时才使用生成的clk信号。
没有任何重大变化。
感谢您的时间。



以下为原文

Austin,
 
i do not understand exactly what you mean with "instantiate it by hand". I would appreciate if you could give me some further informationl or point me an example.
 
Changing to DCM_CLKGEN I get the CLK_STOPPED signal and I use the generated clk signals only when LOCKED = '1' and CLK_STOPPED = '0'. Not any significant changes.
 
Thank you for your time.

一世，
我建议您的100 MHz存在严重问题....
垃圾输入=垃圾输出。
如果一个简单的计数器没有更好的工作，那么100 MHz就会出现问题，或者测量方式出现问题。
简化，直到你得到一个理智和理性的结果！
Austin Lesea主要工程师Xilinx San Jose



以下为原文

i,
 
I suggest there is something seriously wrong with your 100 MHz....
 
Garbage in = garbage out.
 
If a simple counter works no better, then either there is something very wrong with the 100 MHz, or something very wrong with the way you are measuring.  Simplify until you get a sane and rational result!
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

imanolgde写道：
奥斯汀，
我不明白你用“手动实例化”的意思。
如果您能给我一些进一步的信息或者给我一个例子，我将不胜感激。
它意味着“而不是使用向导生成代码，RTF库引用并在代码中实例化原语。”
“实例化”是HDL-land中非常常见的词。
你必须在某个时候遇到它。
通常，您应始终实例化基元，而不是依赖向导来生成代码。
----------------------------是的，我这样做是为了谋生。



以下为原文

imanolgde wrote:
Austin,
 
i do not understand exactly what you mean with "instantiate it by hand". I would appreciate if you could give me some further informationl or point me an example.
 

it means "instead of using the Wizard to generate the code, RTF Libraries Reference and instantiate the primitive in your code."
 
"Instantiation" is a very common word in HDL-land. You must have run across it at some point.
 
In general, you should always instantiate the primitives rather than relying on a Wizard to generate code.
----------------------------Yes, I do this for a living.