VNH5050 Diag ENA引脚的输入电压限制

嗨菲尔，
 你确认这些ENx / DIAGx引脚没有连接到GPIO并且只有上拉电阻吗？
 最好的祝福，
 马尔科



以下为原文







Hi Phil,
do you confirm these ENx/DIAGx pins are not connected to GPIOs and there are only pull-up resistors?
Best regards,
Marco

是..
 
 
当我说::我认为我说得很清楚
 
＆GT;＆GT;＆GT;＆GT;这些引脚没有任何其他连接。
 
 
叹！



以下为原文





Yes..


I think I made that pretty clear when I said::   

>>>>   There is nothing else connected to these pins.


Sigh!

DIAGA / ENA和DIAGB / ENB连接到数字模块（参见数据手册中的图1）。上拉电阻必须连接到Vdd电平（+ 5V）。
 
 
 最好的祝福，
 马尔科



以下为原文





DIAGA/ENA and DIAGB/ENB are connected the digital block (see figure 1 in the datasheet). The pull-up resistor must be connected to Vdd level (+5V).


Best regards,
Marco

你好
 
 
 根据你的回答，我不明白为什么你问我引脚是否连接到外部其他任何东西......因为你说我无法将它们拉到VCC ......
 
 但是，让我进一步探索......
 
 在图1中，图中有一个逻辑块，但没有提到Vdd或5V。
 事实上，如果我辛苦地搜索文档，那么在任何地方都没有提到Vdd，或者芯片使用的是5V逻辑。 （是的，这是电路示例和测试条件所暗示的，但未在任何地方说明）。寻找自己。
 
 此外，在程序框图中，有一个信号钳位功能，这似乎适用于此。在表9中，ENa和ENb线显示输入钳位在5.5和7.5 V之间，1 mA。我认为这是为了保护和调节输入。
 
 因此，如果我在这些输入上使用100K上拉至12V，那么我将输入电流限制为0.06mA，那么输入钳位是否能完成工作并将输入电平降低到合适的电压？如果没有，为什么输入夹在那里？
 
 如果我误解了表格，那么也许一些澄清会有所帮助。
 在这些引脚上指定所需/最大限制（电流和电压）
 
 菲尔。



以下为原文





Hi


Based on your answer, I don't understand why you asked me if the pins were connected to anything else external... since you say I can't pull them up to VCC anyway...

However, let me explore further...

In figure 1, there is a Logic block in the diagram, but no mention of Vdd or 5V.   
In fact, if I painstakingly search the document there is no mention of Vdd anywhere, or that the chip uses 5V logic. (Yes, it's implied by the circuit examples and test conditions, but not stated anywhere).  Search for yourself.

Also, on the block diagram, there is a signal clamp function, which seems to be applicable here.  In table 9, the ENa and ENb lines show an input clamp between 5.5 and 7.5 V at 1 mA. I assume this is to protect and condition the inputs.

So if I use a 100K pullup to 12V on these inputs, then I'm limiting the input current to 0.06mA so wouldn't the input clamps do their job and reduce the input level to an appropriate voltage?  If not, why are the input clamps there?

If I've misinterpreted the sheet, then perhaps some clarification would help out.
Specify the desired/max limits on these pins (Current and voltage)

Phil.

嗨，
 
 你可以设计一个+ 5V的分压器并连接Diag / EN引脚。
 不建议连接到Diag / EN的电压高于+ 5V。
 输入钳位用于保护输入引脚。
 
 最好的祝福，
 马尔科



以下为原文





Hi,

you can design a voltage divider to have +5V and connect the Diag/EN pin.
A voltage level higher than +5V connected to Diag/EN is not suggested.
The input clamp is used to protect the input pins.

Best regards,
Marco