请问我将引脚电压电平约束到lvcmos25的含义是什么？

对于大多数FPGA系列，将有一个“SelectIO用户指南”，其中详细描述了各种IO标准以及该标准所需的Vcco（如果有）。
大多数输出​​标准都需要特定的Vcco，因为这会为驱动程序提供动力
只要输入信号没有被钳位，某些输入标准就可以与任何Vcco一起使用。
这是因为在某些情况下输入接收器由VccAux供电。
所有LVCMOS标准都是相对于Vcco定义的。
输出驱动到导轨。
输入阈值与Vcco成比例。
让工具知道您将使用的正确标准非常重要，这样它们可以防止您将不兼容的IO标准放在同一个库中。
如果您的Vcco不符合标准要求，则IO将无法按预期工作。
对于LVCMOS，这包括：
1）时间安排。
如果Vcco与标准要求不匹配，则输出延迟将与时序报告不同。
2）驱动电流。
驱动电流和输出阻抗与规格不匹配。
通常，较高的Vcco将导致较低的阻抗和较高的驱动电流。
3）输出电压。
正如我所说，输出驱动到轨道。
因此，无论使用何种LVCMOS标准，输出高电压都将遵循Vcco。
4）输入阈值。
关于输出驱动程序实现的一点说
LVCMOS输出使用一组输出FET，它们可以组合在一起以增加驱动和降低阻抗。
随着Vcco的增加，每个FET的阻抗都会降低。
这些工具根据指定的电压和驱动器要求配置所使用的FET数量。
如果Vcco与所选IO标准的规格不匹配，您最终可能会获得比请求的更多或更少的驱动电流。
那么将引脚电压电平约束到lvcmos25的含义是什么？
这意味着您要告诉您承诺将这些引脚所在的Vcco连接到2.5V的工具。
如果您违背诺言，FPGA将违背承诺，为您提供2.5V LVCMOS逻辑电平。
-  Gabor
在原帖中查看解决方案



以下为原文

For most FPGA families there will be a "SelectIO User's Guide" which describes in detail the various IO standards and what Vcco is required (if any) for that standard.  Most output standards require a specific Vcco because this powers the drivers.  Some input standards can work with any Vcco as long as the input signal is not clamped.  That's because in some cases the input receivers are powered by VccAux.
 
All LVCMOS standards are defined relative to Vcco.  The outputs drive to the rails.  The input thresholds are ratiometric to Vcco.  It's important to let the tools know the correct standards you will be using so that they can prevent you from placing incompatible IO standards in the same bank.  If your Vcco does not match the requirements of the standard, the IO will not work as expected.  For LVCMOS this includes:
 
1) Timing.  Output delays will differ from the timing reports if the Vcco doesn't match the requirement for the standard.
 
2) Drive current.  The drive current and output impedance will not match the specs.  Usually a higher Vcco will result in lower impedance and higher drive current.
 
3) Output voltage.  As I said, the outputs drive to the rails.  So the output high voltage will follow Vcco regardless of the LVCMOS standard used.
 
4) Input threshold.
 
One note on output driver implementation.  LVCMOS outputs use a set of output FETs which can be ganged together to increase drive and reduce impedance.  The impedance of each of these FETs gets lower with higher Vcco.  The tools configure the number of FETs used based on the specified voltage and drive reauirements.  If Vcco does not match the spec for the IO standard selected, you may end up with much more or much less drive current than requested.
 
So what's the meaning of constraint the pin voltage level to lvcmos25?
 
 
It means that you are telling the tools that you promise to connect the Vcco of the bank these pins are in to 2.5V.  If you break your promise, the FPGA will break its promise to provide you with 2.5V LVCMOS logic levels.
 
-- GaborView solution in original post

在我看来，输出电压由银行的vco控制。
Michael ------------------------------------------感谢上帝，我遇到了FPGA
.------------------------------------------



以下为原文

in my opinion,the output voltage is controlled by the vco of the bank.Michael

------------------------------------------
Thanks for god,I meet FPGA.
------------------------------------------

查看FPGA系列数据手册。
以绝对值指定的电压不依赖于VCCO。
相对于VCCO或VCCAUX指定的电压将对电源电压敏感（例如，输入切换阈值电压可被描述为VCCO除以2）。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Check the FPGA family datasheet.  Voltages which are specified in absolute terms do not depend on VCCO.  Voltages which are specified relative to VCCO or VCCAUX will be sensitive to the supply voltage (e.g.an input switching threshold voltage may be described as VCCO divided by 2).
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

对于大多数FPGA系列，将有一个“SelectIO用户指南”，其中详细描述了各种IO标准以及该标准所需的Vcco（如果有）。
大多数输出​​标准都需要特定的Vcco，因为这会为驱动程序提供动力
只要输入信号没有被钳位，某些输入标准就可以与任何Vcco一起使用。
这是因为在某些情况下输入接收器由VccAux供电。
所有LVCMOS标准都是相对于Vcco定义的。
输出驱动到导轨。
输入阈值与Vcco成比例。
让工具知道您将使用的正确标准非常重要，这样它们可以防止您将不兼容的IO标准放在同一个库中。
如果您的Vcco不符合标准要求，则IO将无法按预期工作。
对于LVCMOS，这包括：
1）时间安排。
如果Vcco与标准要求不匹配，则输出延迟将与时序报告不同。
2）驱动电流。
驱动电流和输出阻抗与规格不匹配。
通常，较高的Vcco将导致较低的阻抗和较高的驱动电流。
3）输出电压。
正如我所说，输出驱动到轨道。
因此，无论使用何种LVCMOS标准，输出高电压都将遵循Vcco。
4）输入阈值。
关于输出驱动程序实现的一点说
LVCMOS输出使用一组输出FET，它们可以组合在一起以增加驱动和降低阻抗。
随着Vcco的增加，每个FET的阻抗都会降低。
这些工具根据指定的电压和驱动器要求配置所使用的FET数量。
如果Vcco与所选IO标准的规格不匹配，您最终可能会获得比请求的更多或更少的驱动电流。
那么将引脚电压电平约束到lvcmos25的含义是什么？
这意味着您要告诉您承诺将这些引脚所在的Vcco连接到2.5V的工具。
如果您违背诺言，FPGA将违背承诺，为您提供2.5V LVCMOS逻辑电平。
-  Gabor



以下为原文

For most FPGA families there will be a "SelectIO User's Guide" which describes in detail the various IO standards and what Vcco is required (if any) for that standard.  Most output standards require a specific Vcco because this powers the drivers.  Some input standards can work with any Vcco as long as the input signal is not clamped.  That's because in some cases the input receivers are powered by VccAux.
 
All LVCMOS standards are defined relative to Vcco.  The outputs drive to the rails.  The input thresholds are ratiometric to Vcco.  It's important to let the tools know the correct standards you will be using so that they can prevent you from placing incompatible IO standards in the same bank.  If your Vcco does not match the requirements of the standard, the IO will not work as expected.  For LVCMOS this includes:
 
1) Timing.  Output delays will differ from the timing reports if the Vcco doesn't match the requirement for the standard.
 
2) Drive current.  The drive current and output impedance will not match the specs.  Usually a higher Vcco will result in lower impedance and higher drive current.
 
3) Output voltage.  As I said, the outputs drive to the rails.  So the output high voltage will follow Vcco regardless of the LVCMOS standard used.
 
4) Input threshold.
 
One note on output driver implementation.  LVCMOS outputs use a set of output FETs which can be ganged together to increase drive and reduce impedance.  The impedance of each of these FETs gets lower with higher Vcco.  The tools configure the number of FETs used based on the specified voltage and drive reauirements.  If Vcco does not match the spec for the IO standard selected, you may end up with much more or much less drive current than requested.
 
So what's the meaning of constraint the pin voltage level to lvcmos25?
 
 
It means that you are telling the tools that you promise to connect the Vcco of the bank these pins are in to 2.5V.  If you break your promise, the FPGA will break its promise to provide you with 2.5V LVCMOS logic levels.
 
-- Gabor

感谢您的耐心回复。
我读过SelectION ug，我很难理解其中的一切。
回复后，我对IO电压供应了解得更多。
谢谢！



以下为原文

Thanks for your patient reply.
 
I have read the SelectIO ug, It's hard for me to understand all in it.
 
With your reply, I knew more about the IO voltage supply.
 
Thanks!

谢谢，从你的帖子中，我知道了不依赖于VCCO的IO电压



以下为原文

Thanks,

From your post , I got to know the IO voltages not depending on the VCCO