更改时钟频率后，SW Tx UART输出出现乱码

正如标题所说，SW TX UART输出在代码中改变时钟频率之后被篡改。
我正在运行CY8CKIT-042-BLE
ECO＝24兆赫
UART波特率在组件中设置为19200
&代码；
/*内部低功耗振荡器停止，因为它不用于这个项目*/CysSyCLKORITCHOMER（）；//这实际上已经在PSoC Creator的时钟设置中完成了，但是这就是它在代码中是如何实现的。/*设置除法器为ECO，ECO将被用作源当IMO被关闭以节省功率*/CysSyClCluleCeoDeV（CythySylClkE-ECOODIV8）；//-GT；提供3 MHz时钟。SW TX UART组件可接受的最低时钟。/*改变从IMO到ECO的HF时钟源，因为IMO不是必需的，并且可以停止以节省功率*/CysSylClkEngfClkDead（CythySysClkHfClkIKECO）；/*停止IMO以降低功耗*/CysSyClimoCo（）；CySysFlashSetWaitCycles可以在降低SysClk＊CL之后可选地调用。为了提高CPU性能，采用了CK频率。* / CysSysFlash设置（3）；/ /频率为MH/*更新延迟频率，因为时钟频率已改变*/CyDelayFrq（300 000 UL）；
＆代码/代码；
我将一些调试输出到UART，并且在更改时钟之前输出微调。
我认为在改变FRQQ时调用CyDelayFrq应该足够了。
我错过什么了吗？
Br
马丁



     以下为原文
  As title says the SW Tx UART output is garbled after changing the clock frequency in code.
    I am running on the CY8CKIT-042-BLE-A
    ECO = 24 MHz
    UART baud rate set in component to 19200
   
        /* Internal low power oscillator is stopped as it is not used in this project */
     CySysClkIloStop();    // This is actually already done in the clock settings in PSoC Creator, but this is how it is achieved in code.

     /* Set the divider for ECO, ECO will be used as source when IMO is switched off to save power */
     CySysClkWriteEcoDiv(CY_SYS_CLK_ECO_DIV8);   // --> Provides a 3 MHz clock. Lowest clock acceptable for SW Tx UART component.
     /* change HF clock source from IMO to ECO, as IMO is not required and can be stopped to save power */
     CySysClkWriteHfclkDirect(CY_SYS_CLK_HFCLK_ECO);
     /* stop IMO for reducing power consumption */
     CySysClkImoStop();
     
     /* CySysFlashSetWaitCycles can optionally be called after lowering SYSCLK
* clock frequency in order to improve the CPU performance. */
     CySysFlashSetWaitCycles(3); // Frequency in MHz
     /* Update Delay frequency as clock frequency has changed */
     CyDelayFreq(3000000UL);
   
     
    I output some debug to the UART and it outputs fine before i change the clocks.
    I thought that it should be enough to call CyDelayFreq when changing the freq.
    Do I miss something ?
     
    br,
    Martin