如何在XILINX的原理图编辑器中生成200MHZ时钟信号？

一个解决方案，可能是这样的：
图书馆;
使用ieee.std_logic_1164.ALL;
图书馆UNISIM;
使用UNISIM.Vcomponents.ALL;
实体CLK200是 
端口（CLK_50MHZ：在std_logic中; 
CLK_200MHz：输出std_logic; 
RESET_IN：在std_logic中; 
RESET_OUT：out std_logic）;
结束CLK200;
CLK200的架构行为是 
信号DCM_CLK_IN：std_logic; 
信号DCM_CLK_100M：std_logic; 
信号DCM_CLK_200M：std_logic; 
信号RESET：std_logic; 
信号RESET_INV：std_logic; 
信号DCM_LOCKED_OUT：std_logic;
开始 
U1：BUFG端口映射（I => CLK_50MHZ，O => DCM_CLK_IN）;
- 连接DCM_CLK_IN至50 MHz时钟 
U2：BUFG端口映射（I => DCM_CLK_200M，O => CLK_200MHZ）;
- 将DCM输出连接至200 MHz时钟输出 
U3：DCM_SP  - 使用DCM将50MHz时钟乘以200MHz时钟 
通用地图（ 
CLKIN_PERIOD => 20.000，CLKIN_DIVIDE_BY_2 => FALSE，CLK_FEEDBACK =>“2X”， 
CLKFX_DIVIDE => 1，CLKFX_MULTIPLY => 4， 
DFS_FREQUENCY_MODE =>“LOW”，DLL_FREQUENCY_MODE =>“LOW”， 
DESKEW_ADJUST =>“SYSTEM_SYNCHRONOUS”， 
DUTY_CYCLE_CORRECTION => TRUE，FACTORY_JF => X“C080”， 
STARTUP_WAIT => FALSE） 
港口地图（ 
CLKIN => DCM_CLK_IN，CLKFB => DCM_CLK_100M， 
CLK0 =>打开，CLK180 =>打开， 
CLK270 =>打开，CLK90 =>打开， 
CLK2X => DCM_CLK_100M，CLK2X180 =>打开， 
CLKFX => DCM_CLK_200M，CLKFX180 =>打开， 
LOCKED => DCM_LOCKED_OUT，STATUS => open，RST => RESET）; 
U4：INV端口映射（I => RESET，O => RESET_INV）;
- 生成inv重置 
U5：NAND2端口映射（I0 => DCM_LOCKED_OUT，I1 => RESET_INV，O => RESET_OUT）;
- 生成重置
结束行为;



以下为原文

A solution, could be something like this:
library ieee;use ieee.std_logic_1164.ALL;library UNISIM;use UNISIM.Vcomponents.ALL;entity CLK200 is  Port ( CLK_50MHZ   : in std_logic;         CLK_200MHz  : out std_logic;         RESET_IN    : in std_logic;         RESET_OUT   : out std_logic);end CLK200;architecture BEHAVIORAL of CLK200 is  signal DCM_CLK_IN: std_logic;  signal DCM_CLK_100M: std_logic;  signal DCM_CLK_200M: std_logic;  signal RESET: std_logic;  signal RESET_INV: std_logic;  signal DCM_LOCKED_OUT: std_logic;begin  U1: BUFG port map(I=>CLK_50MHZ, O=>DCM_CLK_IN);       -- connect to DCM_CLK_IN to 50 MHz clock  U2: BUFG port map(I=>DCM_CLK_200M, O=>CLK_200MHZ);    -- connect DCM output to 200 MHz clock out  U3: DCM_SP    -- Use DCM to multiply 50MHz clock to 200MHz clock    generic map (      CLKIN_PERIOD => 20.000, CLKIN_DIVIDE_BY_2 => FALSE, CLK_FEEDBACK => "2X",      CLKFX_DIVIDE => 1, CLKFX_MULTIPLY => 4,      DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW",      DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",      DUTY_CYCLE_CORRECTION => TRUE, FACTORY_JF => X"C080",      STARTUP_WAIT => FALSE)    port map (      CLKIN => DCM_CLK_IN, CLKFB => DCM_CLK_100M,      CLK0 => open, CLK180 => open,      CLK270 => open, CLK90 => open,      CLK2X => DCM_CLK_100M, CLK2X180 => open,      CLKFX => DCM_CLK_200M, CLKFX180 => open,      LOCKED => DCM_LOCKED_OUT, STATUS => open, RST => RESET);  U4: INV port map (I=>RESET, O=>RESET_INV);                            -- Generate inv reset  U5: NAND2 port map (I0=>DCM_LOCKED_OUT, I1=>RESET_INV, O=>RESET_OUT); -- Generate reset outend BEHAVIORAL;