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我在CY8C24423 A上使用SPISLAVE模块。这已经工作了好几年,但现在我似乎已经改变了SPI主机中的一些东西,因为PSOC SPILLASS中没有一个响应它。 在检测到芯片选择之后,PSoC将字节加载到SPIbuffer中,然后等待SPITRAN动作完成: MOV A,0x06;MSB第一SPI模式3调用SPISY11START MOV A,% 10101010;将字节加载到SPI调用SPISY11SETUPtxDATA中 现在,等待SPI事务完成呼叫SPISY1ILSTATSTATE和A,0x20;0x20=“SPI完成”状态掩码JZ SPIX等待 但是,尽管没有出现时钟边沿,但是SPIGHEATE循环立即退出。我已经在“范围”上验证了这一点。 有什么想法,为什么循环可能立即退出? 多谢 雨果埃利亚斯 以上来自于百度翻译 以下为原文 Hi, I am using the SPI slave module on a CY8C24423A. This has been working fine for several years, but now I seem to have changed something in the SPI master, because NONE of the PSoC SPI slaves are responding to it. After the chip select is detected, the PSoC loads a byte into the SPI buffer, then waits for the SPI transaction to complete: mov A, 0x06 ; MSB First SPI mode 3 Call SPIS_1_Start Mov A, %10101010 ; Load a byte into the SPI Call SPIS_1_SetupTxData SPI_Wait: ; Now wait for the SPI transaction to complete Call SPIS_1_bReadStatus AND A, 0x20 ;0x20 = 'SPI Done' status mask jz SPI_Wait However, the SPI_Wait loop exits immediately, even though there no clock edges have appeared yet. I have verified this on a 'scope. Any ideas why the loop might exit immediately? Many thanks Hugo Elias |
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和你的不一样,但是我在SPI大师的新版本2Y1上遇到了问题。我认为新版本有一些错误。我使用PSoC开发板,并使用SPI主机和SPI从一个测试,甚至没有连接线外部。每次我给奴隶写的时候,SPI主机都显示SPIMULRXBuffResiZe()当奴隶没有返回任何东西时,它是1。还有什么我需要设置的吗?
以上来自于百度翻译 以下为原文 Not the same thing as yours but I am having problems with the newer version 2_1 of SPI master. I think the newer version has some things wrong. I am using PSoC development board and using the SPI master and SPI slave just for a test without even connecting the wires externally. Everytime I write to the slave the SPI master shows the SPIM_RxBufferSize() to be 1 when there has nothing been sent back by the slave. Is there anything else I need to set up. |
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嗨,雨果。
SPI状态寄存器每当您读取它们时就会被清除,它们保留它们的值。请确认,在该事务或循环之前,状态寄存器已被读取一次,以确保此状态不具有先前事务的状态。 干杯, 普什克 以上来自于百度翻译 以下为原文 Hi Hugo,. SPI Status register gets cleared whenever you read them else they retain their value. Can you please confirm that before this transaction or loop the status register has been read once to ensure that this does not have the status of previous transaction. Cheers, Pushek |
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阿南塔
不管导线是否连接,当主计算机将发送某些东西时,都会在RX缓冲器中接收到。当有线连接的数据已经被正确地设置时,接收的数据将是有效的,否则它可以是任意的随机数据。你需要确保两件事来调试这个问题: 1。接收的数据是否有效。 2。确切地说,主通过发送SCLK脉冲来启动读取。它与你在奴隶中建立数据有什么关系吗? 干杯, 普什克 以上来自于百度翻译 以下为原文 Ananta, Irrespective of the point that wires are connected or not, when master will transmit something will be received in the Rx buffer. When wires are connected data has been properly set up, the received data will be valid else it can be any random data. You need to ensure a couple of things to debug the problem: 1. Whether data received is valid or not. 2. When exactly does the master initiate the read by sending the SCLK pulses. Does it have anything to do with you setting up the data in slave? Cheers, Pushek |
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好了,现在是2013,我正在重温SPI。我正在尝试开发24位ADC芯片的代码。它采用4线SPI总线。如果你还在身边?
电子邮件:PNEELSENG GPROSS.COM 以上来自于百度翻译 以下为原文 Well here it is 2013 and I am revisiting SPI . I am trying to develop code for 24bit ADC IC. It is using 4 wire SPI bus. If you are still around? email: pnielsen@gplains.com |
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自2011以来,发生了重大变化。要提到的是,通过右键单击SPI组件来获得(工作)示例项目的选择的能力。
鲍勃 以上来自于百度翻译 以下为原文 Since 2011 there have been significant changes. To mention is the capability to get a choice of (working) example projects just by a right click on the SPI component. Bob |
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