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大家好，
我正在做一个电路，在木偶上移动一个嘴巴伺服装置，跟踪实时声音输入。我现在的计划是使用模拟块来将音频运行到PGA中，然后通过带通滤波器，最后进入ADC。我一直在使用过滤器向导来设置参数，但是当我查看模拟输出总线上的带通滤波器的输出时，ISEE看起来像是被截断的信号，可能是滤波器采样率。不管怎么说，好像在那个信号上运行ADC不会给我一个可靠的声音幅度。接下来我该做什么，我能为社区提供什么让你看？对于将过滤器向导中的参数设置为什么，有什么建议吗？ 卡盘 以上来自于百度翻译 以下为原文 Hello all, I'm working on a circuit to move a mouth servo on a puppet, tracking live voice input. My current plan is to use the analog blocks to run the audio into a PGA, then through a band pass filter, and finally into an ADC. I have been using the filter wizard to set my parameters, but when I look at the output of the Band pass filter on the analog output buss, I see what looks like the signal chopped up, probably at the filter sample filter rate. Anyway, it looks like running the ADC on that signal would not give me a reliable voice amplitude. What should I do next, and what can I provide to the community for you to look at? Any suggestions for what I should set the parameters in the filter wizard to? -Chuck 
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14个回答
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我在文章标题中得到了错误的部分号。应该是CY8C9466
以上来自于百度翻译 以下为原文 I got the part number wrong in the post title. Should be cy8c29466 |
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特别注意设计中的立柱时钟。中频设计
在2列之间拆分，需要对每个列具有相同的时钟。 也有关于列时钟的过滤模块数据表中的注释 要求。 问候，Dana。 以上来自于百度翻译 以下为原文 Pay particular attention to the column clocks in the design. If design split across 2 columns you need to have same clock to each column. Also there are notes in filter module datasheet about column clock requirements. Regards, Dana. |
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我想我把钟摆好了。这是我的模拟部分的截图。
班纳普 141.5 K 以上来自于百度翻译 以下为原文 I think I have the clocks set up properly. Here is a screenshot of my analog section.
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VC1的时钟设置如何？在过滤器向导中，如果预期特性与标称特性不同，那就不好了。如此多的设置属性，您可能会上传您的项目。那很好。
以上来自于百度翻译 以下为原文 How was a clock setting of VC1? In Filter wizard, If expected characteristics was differ from nominal characteristics, that is no good. So many setting properties, you might be upload your project. That will be good. |
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对于标称1 kHz的BPF，向导报告它想要一个列时钟。
80千赫，VC1可能跑得太快，因为它是一个分频器，范围从1 - 16。关闭CPU时钟，可能太快了。 AdcCc，从数据表中查看它的时钟要求。 以上来自于百度翻译 以下为原文 For a nominal 1 Khz BPF the wizard reports it wants a column clock of 80 Khz, VC1 probably running too fast as it is a divider, ranging from 1 - 16. off CPU clock, probably too fast. And the ADCINC, take a look at its clock requirements from datasheet - |
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谢谢大家。
这是一个精简版的项目。在这点上，我关心的是我在模拟输出总线上看到的信号。我知道很难看到这个白皮书有我的硬件。我的输入有一个小的运算放大器，但是在范围内的信号，和PGA的输出看起来像Iexpect。这只是带通的输出是错误的。我提供了这个项目，这样你就可以看到我的模块设置了。 卡盘 语音跟踪程序 342.9 K 以上来自于百度翻译 以下为原文 Thanks people. Here is a stripped down version of the project. My concern at this point is the signal I see on the analog output bus. I know it is difficult to see this whitout having my hardware. My input has a small op amp, but the signal on the scope, and the output of the PGA looks like what I expect. It is just the output of the bandpass that is wrong. I provide the project so you can see my module settings. -Chuck
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Hi-Cukk时钟设置错误。滤波器的中心频率应与采样频率相关。BPF列时钟可以选择VC1或VC2。除此之外，列时钟为采样频率/ 4，所以可选择的最低频率为24000/64＝375 kHz，采样频率为93.750kHz。当然，你可以找到其他合适的设置。
以上来自于百度翻译 以下为原文 Hi Chuckk Clock setting was wrong. Center frequency of filter should move relate with sampling frequency. BPF column clock can select VC1 or VC2. Beside, Column clock is sampling frequency / 4 So selectable lowest frequency is 24000/64=375KHz And the sampling frequency is 93.750KHz That is it. Of course you can find other setting more suitable。 |
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感谢您的快速故障排除。我明天会测试这个！
我对数字积木很在行。Imuddle通过模拟方，并说明了这一点。 卡盘 以上来自于百度翻译 以下为原文 Thanks you for the fast troubleshooting. I will test this out tomorrow! I'm pretty good with the digital blocks. I muddle through with the analog side, and it shows. -Chuck |
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虽然你的问题似乎被解决了另一个暗示：
ADC时钟和滤波器时钟在您的设计中是相同的。我总是建议你使用不同的列块来选择独立的（或更好的）时钟。 详细说明：从BPF中获得一个滤波值需要多少个时钟周期 需要多少个时钟周期来数字化BPF值？ 如何设置两个时钟，使得所需的转换时间相等。 鲍勃 以上来自于百度翻译 以下为原文 Although your problem seems to be solved another hint: The ADC-clock and filter-clock are the same in your design. I would always suggest you to use different column blocks to have the choice of independent (or better timed) clocks. Elaborate: How many clock cycles does it take to get a filtered value out of the BPF How many clock cycles does it take to digitize that BPF-value How to set both clocks, so that the needed conversion-times are equal. Bob |
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你有2个时钟要求
1）BPF，在向导中，您同时得到采样F和列时钟F。 （考虑到4个X因子）。如果你水平放置放置 你迫使2列时钟的过滤器被迫相同的价值，从而 约束列中的任何其他内容。就像你现在拥有的A/D一样 用BPF的一个极点共享列。所以考虑一条垂直路线。 2）你必须决定在ADCICC上想要什么样的采样率。注意有 你必须观察到的最小值和最大值。 问候，Dana。 以上来自于百度翻译 以下为原文 You have 2 clock requirements - 1) BPF, in the wizard you are given both the sampling f and the column clock f (which takes into account the 4 X factor). If you lay out placement horizontally you force 2 column clocks for the filter to be forced to same value, thereby constraining anything else you have in the column. Like the A/D you now have sharing column with one pole of the BPF. So consider a vertical route. 2) You have to decide what sample rate you want on ADCINC. Note there is both a min and a max associated with ADCINC you have to observe. Regards, Dana. |
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你有2个时钟要求
1）BPF，在向导中，您同时得到采样F和列时钟F。 （考虑到4个X因子）。如果你水平放置放置 你迫使2列时钟的过滤器被迫相同的价值，从而 约束列中的任何其他内容。就像你现在拥有的A/D一样 用BPF的一个极点共享列。所以考虑一条垂直路线。 2）你必须决定在ADCICC上想要什么样的采样率。注意有 你必须观察到的最小值和最大值。 问候，Dana。 以上来自于百度翻译 以下为原文 You have 2 clock requirements - 1) BPF, in the wizard you are given both the sampling f and the column clock f (which takes into account the 4 X factor). If you lay out placement horizontally you force 2 column clocks for the filter to be forced to same value, thereby constraining anything else you have in the column. Like the A/D you now have sharing column with one pole of the BPF. So consider a vertical route. 2) You have to decide what sample rate you want on ADCINC. Note there is both a min and a max associated with ADCINC you have to observe. Regards, Dana. |
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顺便说一下，通常我使用PWM模块来获得BPF列时钟。因为BPF的中心频率将与列时钟成比例地移动。所以，我可以通过改变PWM周期来制作一个可调谐的BPF。早先“采样频率/ 4”的打印错误-& gt；x 4
以上来自于百度翻译 以下为原文 By the way, usually I'm using PWM module to get BPF column clock. Because, center frequency of BPF will move relate with column clock in proportionally. So, I can make a tunable BPF by changing PWM period. Typo of previous post "sampling frequency / 4" ---> x 4 |
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通过PWM调谐产生恒定的Q滤波器，反之亦然。
在音频作品中通常需要的BW。 问候，Dana。 以上来自于百度翻译 以下为原文 Tuning via a PWM creates a constant Q filter, as opposed to constatnt BW, usually desired in audio work. Regards, Dana. |
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