BUFGMUX定时时钟偏差太大

我有两个时钟来自绝对不同的域，C0和C2。
每个时钟都来自自己的BUFG和DCM，所以它们都是很好的时钟，设计可以正常使用。
我有一个BRAM，其中portA用C0时钟计时，portB用C2时钟计时。
这一切都很好。
现在我必须执行以下操作：根据某些控制逻辑，BRAM的portA和portB必须仅由C2提供时钟。
所以我所做的就是把BUFGMUX放在portA前面输入到BRAM的前面。
当控制逻辑为0时，BUFGMUX选择C0，当控制逻辑为1时，则选择C2馈送到BRAM时钟输入的端口A.
我遇到的问题是一个巨大的时钟偏差，因此设置时间违规。
（同时具有BUFGMUX的SYNC和ASYNC设置）
这是一个计时错误的打印输出：
Slack（设置路径）： -  1.317ns（要求 - （数据路径 - 时钟路径偏差+不确定性））来源：number1_memory / U0 / xst_blk_mem_generator / gnativebmg.native_blk_mem_gen / valid.cstr / ramloop [10] .ram.r / s6_init。
ram / TRUE_DP.PRIM18.ram（RAM）目标：test_unit_1 / data0_out_reg0 / q_10（FF）要求：5.000ns数据路径延迟：2.942ns（逻辑电平= 0）（仅限组件延迟超出约束）时钟路径偏差：-2.638
ns（0.963  -  3.601）源时钟：number1mem_clka在0.000ns上升目标时钟：C2在5.000ns时上升时钟不确定度：0.737ns
number1mem_clka是BUFGMUX的时钟输出，进入BRAM的portA时钟输入。
基本上在完成切换之后，number1mem_clka应该与C2在同一时钟域中。
有任何想法吗？



以下为原文

I have two clocks coming from absolutely different domains, C0 and C2. Each of those clocks comes from its own BUFGs and DCMs, so they are good clocks, and design works fine with them.


i have a BRAM where portA clocked with C0 clock,  portB is clocked with C2 clock. it all works good.

now i have to do the following:  depending on some control logic, both portA and portB of BRAM must be clocked only by C2.

so what i did is, just put BUFGMUX in front of portA clock input to BRAM. When control logic is say 0, then C0 is selected by BUFGMUX, when control logic is 1, then C2 is selected to be fed to portA of BRAM clock input.

the problem i have is a huge clock skew, and as a result setup time violation. (with both SYNC and ASYNC settings of BUFGMUX)

Here is a printout of timing error:

Slack (setup path):     -1.317ns (requirement - (data path - clock path skew + uncertainty))
   Source:               number1_memory/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/s6_init.ram/TRUE_DP.PRIM18.ram (RAM)
   Destination:          test_unit_1/data0_out_reg0/q_10 (FF)
   Requirement:          5.000ns
   Data Path Delay:      2.942ns (Levels of Logic = 0)(Component delays alone exceeds constraint)
   Clock Path Skew:      -2.638ns (0.963 - 3.601)
   Source Clock:         number1mem_clka rising at 0.000ns
   Destination Clock:    C2 rising at 5.000ns
   Clock Uncertainty:    0.737ns


number1mem_clka  is clock output from BUFGMUX which goes into portA clock input of BRAM.

basically after a switch is done, number1mem_clka should be in a same clock domain as C2.

any ideas?