测试BUFGMUX原语不可测量的时间要求

嗨赫伯特，
BUFGMUX也存在问题。
这是一个失败的路径FDRE  - > FDRE，其中一个时钟间域路径失败：
Vivado不理解它，它只传播两个时钟并认为两者都可以同时存在，而实际上在任何给定时间只能存在一个。
您需要使用“set_case_analysis”约束来仅分析两个时钟之一，或使用UG903中概述的“set_clock_groups”技术 - 使用约束：
在您的情况下，解决方案是以下约束：
set_clock_groups -asynchronous -group [get_clocks n_2_PLLE2_BASE_inst] -group [get_clocks I]
这将减少故障路径的数量。
然后你的1GHz路径仍然失败。
除了降低时钟速度或选择更快的设备或speedgrade之外，我担心没有简单的解决方案。
-1只是不切断它。
我检查过，当你选择-2时，它符合时间。
顺便说一句，不需要双倍缓冲你的时钟。
只需BUFGMUX即可，无需使用BUFG。
最好的祝福，
德赖斯
--------------------------------------------------
--------------------------------------------------
----------------如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用的帖子并通过点击星标回复导向
在帖子旁边。
在原帖中查看解决方案



以下为原文

Hi Herbert,
 
There is also a problem with the BUFGMUX.
Here is one of the failing paths FDRE -> FDRE with an inter-clock domain path failing:

 
Vivado doesn't understand it, it just propagates both clocks and thinks that both can exist at the same time, while in reality only one can exist at any given time.
You need to either use the "set_case_analysis" constraint to only analyze one of the two clocks or use the "set_clock_groups" technique as outlined in UG903 - Using constraints:
 

 
In your case, the solution is the following constraint:
set_clock_groups -asynchronous -group [get_clocks n_2_PLLE2_BASE_inst] -group [get_clocks I] 
This will reduce the amount of failing paths.
Then your 1GHz paths are still failing. I'm afraid there is no easy solution other than either reducing the clock speed or picking a faster device or speedgrade. -1 just doesn't cut it. I checked and when you select -2, it meets timing.
 
By the way, no need to double buffer your clocks. Just the BUFGMUX suffices, no need to use the BUFGs.
 
 
Best regards,
Dries
 
--------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if the information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented by clicking the star next to the post.
View solution in original post

您使用的是哪种FPGA器件，它是否支持BUFG上的1 GHz时钟？
----------------------------是的，我这样做是为了谋生。



以下为原文

Which FPGA device are you using, and does it support a 1 GHz clock on a BUFG?
----------------------------Yes, I do this for a living.

嗨赫伯特，
BUFGMUX也存在问题。
这是一个失败的路径FDRE  - > FDRE，其中一个时钟间域路径失败：
Vivado不理解它，它只传播两个时钟并认为两者都可以同时存在，而实际上在任何给定时间只能存在一个。
您需要使用“set_case_analysis”约束来仅分析两个时钟之一，或使用UG903中概述的“set_clock_groups”技术 - 使用约束：
在您的情况下，解决方案是以下约束：
set_clock_groups -asynchronous -group [get_clocks n_2_PLLE2_BASE_inst] -group [get_clocks I]
这将减少故障路径的数量。
然后你的1GHz路径仍然失败。
除了降低时钟速度或选择更快的设备或speedgrade之外，我担心没有简单的解决方案。
-1只是不切断它。
我检查过，当你选择-2时，它符合时间。
顺便说一句，不需要双倍缓冲你的时钟。
只需BUFGMUX即可，无需使用BUFG。
最好的祝福，
德赖斯
--------------------------------------------------
--------------------------------------------------
----------------如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用的帖子并通过点击星标回复导向
在帖子旁边。



以下为原文

Hi Herbert,
 
There is also a problem with the BUFGMUX.
Here is one of the failing paths FDRE -> FDRE with an inter-clock domain path failing:

 
Vivado doesn't understand it, it just propagates both clocks and thinks that both can exist at the same time, while in reality only one can exist at any given time.
You need to either use the "set_case_analysis" constraint to only analyze one of the two clocks or use the "set_clock_groups" technique as outlined in UG903 - Using constraints:
 

 
In your case, the solution is the following constraint:
set_clock_groups -asynchronous -group [get_clocks n_2_PLLE2_BASE_inst] -group [get_clocks I] 
This will reduce the amount of failing paths.
Then your 1GHz paths are still failing. I'm afraid there is no easy solution other than either reducing the clock speed or picking a faster device or speedgrade. -1 just doesn't cut it. I checked and when you select -2, it meets timing.
 
By the way, no need to double buffer your clocks. Just the BUFGMUX suffices, no need to use the BUFGs.
 
 
Best regards,
Dries
 
--------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if the information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented by clicking the star next to the post.

hpoetzl写道：
有趣的是，它的工作正常，包括现在根据Vivado满足的所有时序要求，但它在优化过程中给出了相当神秘的信息：
--------------------------------------------------
-------------------------------文件/ var / opt /第9行“create_generated_clock”的必需参数集不正确
AXIOM / PROJ / ZYBO / BUFGMUX / top.xdc ---------------------------------------
------------------------------用法：create_generated_clock [-help] [-name] [-source] [-edges] [
-divide_by] [-multiply_by] [-edge_shift] [-duty_cycle] [-invert] port_pin_list [-add] [-master_clock] [-combinational] [{> | >>}] ----------
--------------------------------------------------
---------文件/var/opt/AXIOM/PROJ/ZYBO/bufgmux/top.xdc-----------第10行“create_generated_clock”的必需参数集不正确 -
--------------------------------------------------
--------用法：create_generated_clock [-help] [-name] [-source] [-edges] [-divide_by] [-multiply_by] [-edge_shift] [-duty_cycle] [-invert] port_pin_list [ -
添加] [-master_clock] [-combinational] [{> | >>}] --------------------------------
---------------------------
----------
请注意，时钟已成功重命名为clk0 / clk1并正确列出这些名称。
再次感谢，
赫伯特
嗨赫伯特，
这是一个已知的“bug”，如果它甚至值得称之为;）
不用担心，这在2014年得到了解决
最好的祝福
德赖斯
--------------------------------------------------
--------------------------------------------------
----------------如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用的帖子并通过点击星标回复导向
在帖子旁边。



以下为原文

hpoetzl wrote:
 
The interesting part is, that works just fine, including all timing requirements now being met according to Vivado, but it gives a rather cryptic message during optimization:
 
---------------------------------------------------------------------------------
incorrect set of required parameters for "create_generated_clock" at line 9 of file /var/opt/AXIOM/PROJ/ZYBO/bufgmux/top.xdc
---------------------------------------------------------------------
Usage:
  create_generated_clock
    [-help]
    [-name ]
    [-source ]
    [-edges ]
    [-divide_by ]
    [-multiply_by ]
    [-edge_shift ]
    [-duty_cycle ]
    [-invert]
    port_pin_list
    [-add]
    [-master_clock ]
    [-combinational]
    [{>|>>} ]
---------------------------------------------------------------------
incorrect set of required parameters for "create_generated_clock" at line 10 of file /var/opt/AXIOM/PROJ/ZYBO/bufgmux/top.xdc
---------------------------------------------------------------------
Usage:
  create_generated_clock
    [-help]
    [-name ]
    [-source ]
    [-edges ]
    [-divide_by ]
    [-multiply_by ]
    [-edge_shift ]
    [-duty_cycle ]
    [-invert]
    port_pin_list
    [-add]
    [-master_clock ]
    [-combinational]
    [{>|>>} ]
---------------------------------------------------------------------


Note that the clocks are successfully renamed to clk0/clk1 and properly listed with those names.
 
Thanks again,
Herbert

Hi Herbert,
 
that's a known "bug" if it's even worth calling that ;)
No worries, that's resolved in 2014.1
 
 
best regards
Dries
--------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if the information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented by clicking the star next to the post.

嗨赫伯特，
道歉，不知怎的，我没有看到那个消息。
我会针对此提交CR。
目前你可以忽略这一点：我看到在route_design clk0和clk1被识别之后。
最好的祝福
德赖斯
--------------------------------------------------
--------------------------------------------------
----------------如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用的帖子并通过点击星标回复导向
在帖子旁边。



以下为原文

Hi Herbert,
 
apologies, somehow I didn't see that message.
 
I will file a CR against this.
For the moment you can simply ignore this: I see that after route_design clk0 and clk1 are recognized.
 
 
Best regards
Dries
--------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if the information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented by clicking the star next to the post.

实际上，在提交申请时，我注意到这是Vivado 2014.2中已解决的已知问题。
有一个答案记录：AR60269
Vivado 2014.2计划于6月发布。
最好的祝福
德赖斯
--------------------------------------------------
--------------------------------------------------
----------------如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用的帖子并通过点击星标回复导向
在帖子旁边。



以下为原文

Actually, while filing, I noticed that it's a known issue that is resolved in Vivado 2014.2.
There is an answer record about it: AR60269
 
Vivado 2014.2 is scheduled for release in June.
 
 
Best regards
Dries
--------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if the information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented by clicking the star next to the post.