请问Spartan板或Virtex有低压系列吗？

Spartan-6和Virtex-6都具有可订购的低功率设备（-1L速度等级）。
Vccint可以在V6中降至0.9V（典型值），在S6中降至1.0V（典型值）。
据我所知，这些设备还没有可用的板。
我不确定你通过放弃Vccint来运行什么实验。
但请注意，Xilinx仅保证操作和数据手册规格在推荐工作条件下的最小Vccint编号。
除此之外的任何事情都是你自己的。
另外，请注意Vdrint  - 保存CMOS配置锁存（CCL）内容和RAM数据所需的电源电压。
我相信这个值大约是1.0V，所以听起来你的操作低于那个。
-Eric
在原帖中查看解决方案



以下为原文

Both Spartan-6 and Virtex-6 have Lower Power devices that can be ordered (-1L speed grade).  The Vccint can be dropped to 0.9V typ in V6, and 1.0V typ in S6.  There are not any boards available with these devices yet, though, to my knowledge. 
 
I'm not sure what experiments you are running by dropping Vccint.  Be aware, though, that Xilinx will only guarantee operation and data sheet spec to the min Vccint number in the Recommended Operating conditions.  Anything beyond that is on your own.  Also, be aware of the Vdrint - the supply voltage level necessary for preserving CMOS configuration latch (CCL) contents and RAM data.  That value is around 1.0V I believe, so it sounds like you are operating below that.
 
-Eric
 
View solution in original post

Spartan-6和Virtex-6都具有可订购的低功率设备（-1L速度等级）。
Vccint可以在V6中降至0.9V（典型值），在S6中降至1.0V（典型值）。
据我所知，这些设备还没有可用的板。
我不确定你通过放弃Vccint来运行什么实验。
但请注意，Xilinx仅保证操作和数据手册规格在推荐工作条件下的最小Vccint编号。
除此之外的任何事情都是你自己的。
另外，请注意Vdrint  - 保存CMOS配置锁存（CCL）内容和RAM数据所需的电源电压。
我相信这个值大约是1.0V，所以听起来你的操作低于那个。
-Eric



以下为原文

Both Spartan-6 and Virtex-6 have Lower Power devices that can be ordered (-1L speed grade).  The Vccint can be dropped to 0.9V typ in V6, and 1.0V typ in S6.  There are not any boards available with these devices yet, though, to my knowledge. 
 
I'm not sure what experiments you are running by dropping Vccint.  Be aware, though, that Xilinx will only guarantee operation and data sheet spec to the min Vccint number in the Recommended Operating conditions.  Anything beyond that is on your own.  Also, be aware of the Vdrint - the supply voltage level necessary for preserving CMOS configuration latch (CCL) contents and RAM data.  That value is around 1.0V I believe, so it sounds like you are operating below that.
 
-Eric
 

你好埃里克，
感谢您的回复。
我知道低电压时工艺变化很大，电路板不会按预期给出结果。
但我们的实验目标是最大化工艺变化，并尽量减少噪音，温度和其他外部因素造成的变化。
这就是为什么我想知道是否有任何低压FPGA，以便我们只能利用工艺变化。
问候，
卡努



以下为原文

Hello Eric,
 
Thanks for your reply. I am aware that process variations are high at low voltage and the board will not give the results as expected. But aim of our experiment is to maximize the process variation and minimize variation due to noise, temperature and other external factors. This is why I wondering if there are any low voltage FPGAs so that we can take advantage of only the process variation.
 
Regards,
Kanu

卡努
您的要求不是很清楚。
您是否正在为某些实验寻找一组过程角点低阈值零件？
如果是这样，您将无法从销售分销渠道获取它们。
如果您正在寻找的是一组在过程shmoo图中紧密分组的零件，那么您最简单的方法就是从单个晶圆加工批次中获取一组零件。
批次之间的生产过程变化很大，但在一个批次内，过程特征可预测地是统一的。
如果您需要特殊屏蔽部件，则需要通过Xilinx客户经理进行安排。
我已经请求并从供应商那里获得了这些特别筛选的部件（不是来自Xilinx），但我当时正在为一家数量庞大的$$公司工作。
您可能需要通过大学部门负责人（或更高级别）向您的项目提出要求，以使Xilinx感兴趣。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
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以下为原文

Kanu,
 
Your request is anything but clear.  Are you looking for a set of process corner case low-threshold parts for some experiments?  If so, you won't get them from the sales distribution channel.
 
If all you are looking for is a set of parts which are tightly grouped in a process shmoo plot, then your easiest path to that would be procuring a set of parts from a single wafer process lot.  Production process variations from lot to lot are large, but within a single lot the process characteristics are predictably uniform.
 
If you want specially screened parts, you'll need to arrange for them through a Xilinx account manager.  I've requested and received such specially screened parts from vendors (not from Xilinx, though), but I was working for a multi-billion $$ company in a high-volume business at the time.  You may need to make your parts request through university department heads (or higher) to interest Xilinx in your project.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
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大家好，
虽然这是一个老线程，但我在继续上述讨论时有疑问。
这就是为什么我以为我会在这里发帖。
我将Spartan 3E Starter套件置于低电压状态。
但是，如上所述，它没有产生稳定的结果。
我只是想知道FPGA芯片的哪个部分受到低电压的影响。
我阅读了一些关于亚阈值FPGA的研究论文。
他们说FPGA的低电压操作具有挑战性主要是因为有三个原因：
- 变化会影响电路级参数，如电流，阈值电压，延迟等
- 由于变化，互连设计变得困难。
- 配置存储器受到影响，需要高阈值电压晶体管才能工作。
如果我能知道其他人的想法会很有帮助。
FPGA的哪些其他功能/部分应该受到影响？为什么？
谢谢，
卡努



以下为原文

Hi All,
 
Though this is an old thread, but I have have question in continuation with the above discussion. This is why I thought I will post here. I subjected Spartan 3E Starter's kit to low voltage. However, as mentioned above it did not generate stable results. I was just wondering what part of FPGA chip is affected by the low voltage. I read some of the research papers on subthreshold FPGA. They say that low voltage operation of a FPGA is challenging mainly because ot three reasons :
 
- Variations affect circuit level parameters such as current, threshold voltage, delay, etc
- Interconnect design becomes difficult because of variations.
- Configuration memory is affected and it need high threshold voltage transistors to function.
 
It would be helpful if I could know what others think. Which other function/part of FPGA should be affected  and why ?
 
Thanks,
Kanu

请描述您为降低电压和实验结果所采取的确切步骤。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

Please describe the exact steps that you took to lower the voltage and the results of this experiment.------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

嗨mcgett，
为了降低芯片的电压，移除JP7以断开与1.2V的连接。
外部电压源与JP7引脚相连。
此外，在进行低电压的完整实验之前，确保小电路确定环形振荡器在电路板上以如此低的电压工作。
在连接到电路板的一个I / O引脚的示波器上观察到环形振荡器频率。
实验设置包括一组通过MUX连接到一个32位计数器的环形振荡器。
基本目标是记录每个环形振荡器的计数器值。
然而，结果似乎表明，一旦我们增加RO的数量，计数器值就会变得不可靠。
我在想什么应该是这种行为的可能解释。
一种可能性是Eric指出的配置存储器。
另外，我知道FPGA芯片并不适用于0.7V这样的低电压。
但是，我在想它背后的其他原因是什么？
是因为记忆吗？
或其他一些电路部件也会受到影响？
谢谢，
卡努



以下为原文

Hi mcgett,
 
To lower the voltage of the chip, JP7 was removed to disconnect from 1.2V. An external voltage source was tied to JP7 pins.
 
Also, before proceeding with complete experiment at low voltage, it was made sure that a small circuit say a ring oscillator is working at such low voltage on the board. Ring oscillator frequency was observed on oscilloscope connected to one of the I/O pins of the board.
 
The experiment set up consisted of a bunch of ring oscillators connected to one 32-bit counter through a MUX. The basic aim was to record the counter values for each ring oscillator. However, the results seemed to suggest that once we increase the number of ROs, the counter values turn to be unreliable.
 
I was thinking what should be a possible explanation for this behaviour.  One possibility is configuration memory as pointed by Eric. Also, I do understand that the FPGA chip is not meant to work at such low voltage as 0.7V. However, I was thinking what could be other reason behind it ? Is it only because of memory ? or some other circuit parts are affected too ?
 
Thanks,
Kanu

为什么在将FPGA电源电压降低到故障点时首先解释FPGA内的哪些器件已损坏很重要？
您如何知道您的测试是否足够全面以找到首次失败的点？
如果您认真了解逻辑器件的低压限制，您认为您不应该构建自己的测试设计并描述裸（未封装）骰子吗？
对于您似乎正在寻求的东西，弄乱复杂的封装和缓冲设备似乎是浪费时间和精力。
您应该控制测试电路设计和半导体工艺。
如果没有这种最低程度的控制和访问，您就会试着了解内燃机如何使用螺丝刀，戴着连指手套。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Why it important to explain which devices inside an FPGA were corrupted first, when reducing the FPGA supply voltage to the point of failure?
 
How do you know your tests are comprehensive enough to find the point of first failure?
 
If you are serious about understanding the low-voltage limits for logic devices, don't you think you should be building your own test designs and characterising the bare (unpackaged) dice?  For what you seem to be seeking, messing around with complex packaged and buffered devices seems such a waste of time and effort.  You should be controlling the test circuit designs and the semiconductor process.  Without this minimal level of control and access, you are trying to understand how internal combustion engines work using nothing more than a screwdriver, while wearing mittens.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

嗨鲍勃，
我完全理解你的观点。
我确实理解，即使不打算让电路在低电压下工作也是浪费时间。
我感谢大家对此主题的帮助。
我很抱歉打扰我的问题。
问候，
卡努



以下为原文

Hi Bob,
 
I definitely understand your point of view. I do understand that it is a waste of time to make the circuit work at low voltage even though it is not meant to.
 
I appreciate everyone help on this thread. I am sorry to bother with my questions.
 
Regards,
Kanu

八个月后，是什么让你信服的？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Eight months later, what convinced you?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

>为了降低芯片的电压，JP7被移除以断开与1.2V的连接。
外部电压
>来源与JP7引脚相关......然而，结果似乎表明一旦我们增加
> RO的数量，计数器值变得不可靠。
设备中的更多逻辑将消耗更多功率，从而导致更多电源从FPGA降至FPGA，FPGA逻辑电压更低。
>另外，我知道FPGA芯片并不适用于0.7V这样的低电压。
这是正确的，它被设计为在1.2V的更高电压下工作
>但是，我在想它背后的其他原因是什么？
是因为记忆吗？
>或其他一些电路部件也会受到影响？
如果不确切知道正在使用哪些资源（你的描述还不够），任何东西都是纯粹的推测。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> To lower the voltage of the chip, JP7 was removed to disconnect from 1.2V. An external voltage
> source was tied to JP7 pins......However, the results seemed to suggest that once we increase
> the number of ROs, the counter values turn to be unreliable.
 
More logic in the device will consume more power resulting in more drop from your power supply to the FPGA with the FPGA logic seeing an even lower voltage.
 
> Also, I do understand that the FPGA chip is not meant to work at such low voltage as 0.7V.
 
That's right it was designed to operate at a much higher voltage at 1.2V
 
>  However, I was thinking what could be other reason behind it ? Is it only because of memory ?
> or some other circuit parts are affected too ?
 
Without knowing exactly what resources are being used (your description is not enough) anything would be pure speculation.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

嗨mcgett，
感谢您的回复。
我已经为32个RO和128个RO电路附加了设备利用率截图。
每个RO在一个CLB中作为硬宏放置，其输出通过MUX进行计数。
计数器值使用UART模块发送到计算机。
可以看出，使用的4输入LUT的数量从附件中增加了5％至17％。
我想知道在低电压下这么多的利用率是否过高？
如果我的解释不足以得出关于电路在低电压下的行为的结论，请告诉我。
谢谢，
卡努



以下为原文

Hi mcgett,
 
Thanks for your reply. I have attached the device utilization screenshot for 32 ROs and 128 ROs circuits. Each RO is placed as hard macro in one CLB and with its output going to counter through MUX. The counter values were sent to a computer using UART module.
 
It can be seen that number of 4-input LUTs used inceases from 5% to 17%  from  the attachment. I was wondering if this much of utilization is too much at low voltage ? Please let me know if my explanation is not enough to conclude on circuit's behaviour at low voltage.
 
Thanks,
Kanu