怎么使用BUFG降低时钟速度

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以下为原文

Why is 4'b0110 used to establish a 3Mhz clock?
 
The important requirement is that the clock enable is a single-cycle pulse which occurs once every 16 (50MHz) clock cycles.  A clock enable is not a clock.  REPEAT: a clock enable is NOT a CLOCK.
 
Example:
 

• Two 8-bit counters, both clocked with the same 50MHz clock.
  

• One counter is free-running.  It counts at a 50MHz frequency.
  

• The other other counter has a clock enable signal.  When the clock enable is '1', the counter clocks.  When the clock enable is '0' the counter maintains current value (state).
  

• The clock enable signal maintains a repeating sequence: 15 cycles of '0' followed by a single cycle of '1'.
  

• The second counter increments at 1/16 of the frequency of the free-running counter, or 50/16 MHz (roughly 3MHz)
  

• The frequency of bit[4] of the free-running counter matches the frequency of bit[0] of the second counter.
  

• The frequency of bits[7:5] of the free-running counter match the frequency of bits[4:1] (respectively) of the second counter.
  

• The clock enable is not a clock, so it does not appear in the process sensitivity list of the second counter.
  

• On the clock's positive edge, the current counter bit values and the clock enable are all evaluated to determine the process function -- and counter's next state.
  

Sclkena is non-blocking, so the value won't be updated until the next clock, which would make the value 4'b0111 when Sclkena is checked thus generating a 7Mhz clock.
 
Your description is incorrect.  The register delays the clock enable by a clock cycle, its frequency is not changed.  I do not understand your meaning for the phrase 'when Sclkena is checked'.
 
Wouldn't you want an initial value of 4'b01111 4'b1111 for a 3MHz clock that is sensitive on a positive edge?
 
Please explain why you think this.  Think in terms of hardware:  gates (or logic functions) and clocked registers.
 
What is the purpose of count_up and count_down?
 
You are referring to a design application in the linked thread which is a separate logic design problem.  We're discussing clock enables, let's pursue this one topic without the distraction of someone else's unrelated logic design problem.
 
If I understand your method correctly, is this is the a correct code for generating a 1Hz and 2Hz clock and making two LEDs blink on/off accordingly?
 
Nicely done, I approve, with one problem:  the counter needs to divide by 25,000,000(d) instead of divide by 2^25. Here is an important change:
 
Replace this
always @(posedge CLK_50MHZ) clk_counter <= clk_counter + 1;  // increment counter
 
always @(posedge CLK_50MHZ)
    begin
        ENABLE_CLK_1HZ <= (clk_counter[25:0] == 50000000-1);    // Enable 1Hz Clock
        ENABLE_CLK_2HZ <= (clk_counter[24:0] == 25000000-1);    // Enable 2Hz Clock
    end
 
with this:
always @(posedge CLK_50MHZ)
  if (clk_counter[24:0] == 25000000-1)  // divide by 25,000,000 to 2Hz, terminal count?
    begin
      clk_counter[24:0]  <= 0;  // wrap to 0

      clk_counter[25]  <= ~clk_counter[25];  // toggle bit[25] at 2Hz rate -- result is 1Hz
      ENABLE_CLK_2HZ <= 1; // Enable 2Hz Clock
      ENABLE_CLK_1HZ <= clk_counter[25]; // Enable 1Hz Clock

    end
  else  // in between 2Hz pulses
    begin
      clk_counter[24:0] <= clk_counter[24:0] + 1; // increment 2Hz counter
      ENABLE_CLK_2HZ <= 0; // Disable 2Hz Clock
      ENABLE_CLK_1HZ <= 0; // Disable 1Hz Clock

   end
 
Also when executing the always statements in this fashion (three always statements sensitive to the same signal), are they done in parallel or sequentially?
 
Software is executed sequentially, hardware operates in parallel.  We hardware snobs prefer the term 'concurrent'.  Sequenced logic in a single clocked process is called a state machine.  Any timing dependency between processes in hardware design must be explicit -- by design.
 
I'm going to re-read the first few chapters of the book I got on Verilog, my next goal is to use the 2x16 LCD display screen on my development board.

Don't lose sight of the fact that Verilog is a language.  It is a tool for describing hardware.  Learning hardware (and logic design) is not the same thing as learning Verilog.  Learning Verilog is not enough, you must also learn hardware.  In many ways, your life would be simpler if you learned hardware first, and then learned Verilog.  Always you must use the language correctly to generate the intended hardware design.  Understanding the desired end result is required to understand how Verilog is to be used.
 
-- Bob Elkind
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8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.View solution in original post

BUFG缓冲区用于在整个FPGA中分配内部时钟。
它们不是高电流输出缓冲器/驱动器。
有关各种输出引脚驱动程序配置，请参阅Spartan 3x系列文档的IOSTANDARD部分。
通常，输出和输入配置（和引脚分配）在项目.UCF文件中定义。
您应该花一些时间来查看可从Xilinx网站下载的参考设计之一。
你可以从检查各种零碎的东西中学到很多东西。
以下是一些快速的课程：7小时的Verilog旅行：
1.使用有意义且可识别的信号名称。
2.在代码中添加描述您意图的注释。
当你在睡眠不足昏迷中花费20个小时编写代码后早上醒来时，信号名称和注释将极大地提醒你在最后的最后2个小时内你在思考（或不思考）的是什么
屈服于睡眠不足。
这些评论还鼓励您一次计划实施多于一行或两行代码。
最后，你的'触发信号'是什么意思？
以下是代码清理示例：
模块核心（ 
输入clk3Mhz，// 3MHz输入时钟 
输出reg led = 0）;
// LED输出驱动，3Hz，低= ON 
reg [31：0] clk_divide = 0;
//时钟分频器，只需要20位
总是@（posedge clk3Mhz）开始 
if（clk_divide == 32'h000F423F）//数量达到100万 -  1？ 
开始 
clk_divide
Xilinx合成器几乎总是推断（插入）BUFG时钟缓冲器，用于设计中用作全局时钟的信号（clk3Mhz，在上例中）。
在上面的示例代码中，需要注意产生具有50％占空比LED输出的百万分之一计数器。
简单地除以2 ^ 20二进制计数器会简单得多，在这种情况下，clk_divide [19：0]的clk_divide [19]对于LED输出项就足够了。
这是一个更简单的示例实现：
模块核心（ 
输入clk3Mhz，// 3MHz输入时钟 
输出线led）;
// LED输出驱动，大约3Hz，低= ON 
reg [19：0] clk_divide = 0;
//时钟分频器，只需要20位
总是@（posedge clk3Mhz）clk_divide
最后，在这些论坛中寻求帮助时，您必须尽可能具体地了解要解决的问题的性质。
在你的第一篇文章中你写了'但它对我不起作用'。
经过30多年的婚姻，这种程度的模糊仍然令人讨厌。
尝试具体说明问题 - 它的作用以及您希望它做什么。
对于试图接听您电话的人来说，这是一个很大的（也是必要的）帮助。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

BUFG buffers are for distribution of internal clocks throughout the FPGA.  They are not high-current output buffer/drivers.
 
See the IOSTANDARD sections of the Spartan 3x family docs for the various output pin driver configurations.  Generally, the output and input configurations (and pin assignments) are defined in the project .UCF file.  You should take some time to review one of the reference designs available for download from the Xilinx website.  You can learn quite a bit from checking out the various bits and pieces.
 
Here are a few quick lessons to learn, 7 hours into your Verilog travels:
 
1.  Use meaningful and recognisable signal names.
 
2.  Add comments to your code which describe your intent.
 
When you wake up in the morning after having spent 20 hours writing code in sleep-deprived stupor, the signal names and comments will greatly help to remind you what the heck you were thinking (or not thinking) in the last 2 hours before you finally succumbed to lack of sleep.  The comments also encourage you to plan your implementation more than one or two lines of code at a time.
 
Finally, what do you mean by 'a triggerable signal' ?
 
Here is an example cleanup of your code:
 
module Core(  input clk3Mhz,   // 3MHz input clock  output reg  led=0 );    // LED output drive, 3Hz, low = ON  reg [31:0] clk_divide = 0;  // clock divider, only 20 bits neededalways @(posedge clk3Mhz) begin  if (clk_divide == 32'h000F423F)  // count reached 1 million - 1?   begin     clk_divide <= 0;  // then loop to zero after 1 million counts     led <= 0;         // turn on the LED   end  else  // counter hasn't yet reached terminal count   begin       clk_divide <= clk_divide + 1;  // count to 1 million - 1     if (clk_divide == 32'h0007A11F)  // count reached 500k -1 ?       led <= 1;       // turn off the LED   endendmoduleThe Xilinx synthesiser will almost always infer (insert) BUFG clock buffers for signals which are used as global clocks in your design (clk3Mhz, in the above example).
 
In the above example code, pains are taken to generate a divide-by-million counter with a 50% duty cycle LED output.  A simple divide by 2^20 binary counter would have been much simpler, in which case clk_divide[19] of clk_divide[19:0] would be sufficient for the LED output term.
 
Here's a much simpler example implementation:
module Core(  input clk3Mhz,   // 3MHz input clock  output wire led );    // LED output drive, roughly 3Hz, low = ON  reg [19:0] clk_divide = 0;  // clock divider, only 20 bits neededalways @(posedge clk3Mhz)  clk_divide <= clk_divide + 1;  // 20-bit counterassign led = clk_divide[19];       // roughly 3Hz, 50% duty cycleendmodule 
Finally, when asking for help in these forums, it is essential that you are as specific as possible with the nature of the problem to be solved.  In your first post you wrote 'but it doesn't work for me'.  After 30+ years of marriage, this degree of vagueness is still annoying.   Try to be specific about the problem -- what it does and what you expect it to do.  This is a big (and necessary) help for anyone who tries to answer your call.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

在你的第一个例子清理我的代码时，我在reg led = 0上得到了'led'的非法重新声明;
// LED驱动器的输出寄存器，是否有严格设置允许编译？
要编译，我必须创建一个assign语句，例如：
模块核心（输入CLK_50MHZ，// 50 MHz输入时钟输出导线）;
// LED输出驱动，1Hz闪烁开/关，ON = 1 reg [31：0] clk_counter = 0;
//时钟计数器，50Mhz后复位为零reg_state = 0;
// 1 = ON，0 = OFFalways @（posedge CLK_50MHZ）如果（clk_counter == 50000000）// 50MHz开始clk_counter
除非这是预期的行为。
当我阅读上面的帖子时，在我看来，通过使用BUFG，作者可以任意配置任何寄存器作为时钟信号，可以将其添加到always语句的灵敏度列表中。
这就是我所说的“触发信号”。
我也对DCM进行了总结，所以我很清楚，使用DCM（数字时钟管理器）在这种情况下是不适用的，因为它不能将50MHz时钟减慢到1Hz，最高支持的除数是16（~3.125）
兆赫）。
当我使用时钟频率合成器时，Fout（MHz）范围是5.000Mhz  -  311.00Mhz
我的开发板的约束文件说：
＃====时钟输入（CLK）====
NET“CLK_50MHZ”LOC =“C9”|
IOSTANDARD = LVCMOS33;
＃GCLK10
＃定义50 MHz振荡器的时钟周期（40％/ 60％占空比）
NET“CLK_50MHZ”周期= 20.0ns高40％;
如果我使用DCM，我可以使用占空比校正将占空比标称为50％，对吗？



以下为原文

In your first example cleanup of my code, I get an  Illegal redeclaration of 'led' on reg        led = 0;         // output register for LED drive, is there a strictness setting to allow this to compile?  To compile I must create an assign statement eg:



module Core(
    input CLK_50MHZ,   // 50 MHz input clock
    output wire led );    // LED output drive, 1Hz blink on/off, ON = 1

    reg [31:0] clk_counter = 0;  // clock counter, resets after 50Mhz to zero
    reg led_state = 0;            // 1 = ON, 0 = OFF

always @(posedge CLK_50MHZ)
    begin
        if(clk_counter == 50000000)    // 50MHz
            begin
                clk_counter <= 0;                // reset counter after 50Mhz so the led state can be changed
                led_state <= ~led_state;    // invert the state of the LED (ie: turn on or off depending on the previous state)
            end
        else
            begin
                clk_counter <= clk_counter + 1;  // 32-bit counter
            end
    end

    assign led = led_state;

endmodule 
Unless this is the expected behavior.
 
When I read the above thread it appeared to me that by using BUFG the author could arbitrarily configure any register as a clock signal which could be added to the sensitivity list of an always statement. That's what I meant by "trigger-able signal".
 
I also sumbled upon DCM's, so I'm clear, using a DCM (Digital Clock Manager) wouldn't be applicable in this case because it can't slow a 50MHz clock down to 1Hz, the highest supported divisor is 16 (~3.125MHz). When I use the Clock Freqency Synthesizer the Fout (MHz) range is 5.000Mhz - 311.00Mhz
 
the constraints file for my development board says:
# ==== Clock inputs (CLK) ====NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ; # GCLK10# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%; 
If I use the DCM I can nomilze the duty cycle to 50% with Use Duty Cycle Correction, correct?

您的代码将其声明为wire，然后将其声明为reg，这就是解析器为您提供错误的原因。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

Your code declared it as wire and then as a reg which is why the parser is giving you an error.------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

在你的第一个例子清理我的代码时，我在reg led = 0上得到了'led'的非法重新声明;
// LED驱动器的输出寄存器，是否有严格设置允许编译？
要编译，我必须创建一个assign语句，例如：
你了解我的例子中的原始错误吗？
一旦声明了变量led（在OUTPUT语句中），就不能重新声明它（在后续的reg语句中）。
我已经纠正了原帖。
当我阅读上面的帖子时，在我看来，通过使用BUFG，作者可以任意配置任何寄存器作为时钟信号，可以将其添加到always语句的灵敏度列表中。
这就是我所说的“触发信号”。
正确...过程敏感性列表由模拟器用于调度（您称之为'触发'）过程的评估。
这不会（通常）影响合成硬件，除非您推断寄存器和锁存器。
感谢您澄清对“触发器”一词的使用。
术语“触发器”在逻辑设计中经常使用，但我不记得“触发器”与此含义一起使用。
我学到了一些东西。
存在听起来合法的风险，寄存器不是信号，因此寄存器不能配置为时钟。
您想使用寄存器输出作为时钟吗？
这并不罕见，特别是在通过划分较高频率时钟产生的非常低频时钟的情况下。
另一方面，您是否考虑过使用3Hz时钟使能来提供与3MHz时钟相同（或更好）的等效功能？
如果你有时间和耐心，这里有两个线程（一个很长）讨论使用时钟使能和生成附加时钟之间的权衡。
线程1
线程2
如果我使用DCM，我可以使用占空比校正将占空比标称为50％，对吗？
来自UG331：
Spartan-3E和扩展的Spartan-3A系列FPGA输出时钟调节
DCM自动调节Spartan-3E和扩展Spartan-3A系列FPGA上的所有时钟输出，使其具有50％的占空比。
您确定40/60％的时钟占空比是您设计中的一个重要问题吗？
如果您只使用一个时钟边沿（例如时钟上升沿），50MHz时钟的60/40％占空比不应该让您担心。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
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以下为原文

In your first example cleanup of my code, I get an  Illegal redeclaration of 'led' on reg led = 0;         // output register for LED drive, is there a strictness setting to allow this to compile?  To compile I must create an assign statement eg:
 
Do you understand the original error in my example ?  Once the variable led is declared (in an OUTPUT statement), it cannot be re-declared (in the subsequent reg statement).  I've corrected the original post.
 
When I read the above thread it appeared to me that by using BUFG the author could arbitrarily configure any register as a clock signal which could be added to the sensitivity list of an always statement. That's what I meant by "trigger-able signal".
 
Right...  the process sensitivity list is used by the simulator for scheduling (what you call 'triggering') evaluation of the process.  This does not (usually) affect the synthesised hardware, unless you are inferring registers and latches.  Thank you for clarifying your use of the term 'trigger'.  The term 'trigger' is used quite often in logic design, but I don't recall 'trigger' used with this meaning.  I've learned something.
 
At the risk of sounding legalistic, a register is not a signal, and therefore a register cannot be configured as a clock.  Do you want to use a register output as a clock?  This isn't unusual, especially in the case of very low frequency clocks generated by dividing a higher frequency clock.  On the other hand, have you considered the use of a 3Hz clock enable for providing the same (or better) equivalent function as a 3MHz clock?
 
If you have the time and patience, here are two threads (one is quite long) which discuss the tradeoffs between using clock enables and generating additional clocks.
 
thread1
thread2
 
If I use the DCM I can nomilze the duty cycle to 50% with Use Duty Cycle Correction, correct?
 
From UG331:
 
Spartan-3E and Extended Spartan-3A Family FPGA Output Clock Conditioning

The DCM automatically conditions all clock outputs on Spartan-3E and Extended Spartan-3A family FPGAs so that they have a 50% duty cycle.
 
Are you sure that 40/60% clock duty cycle is an important concern in your design?  If you are using only one clock edge (e.g. rising clock edge), 60/40% duty cycle of a 50MHz clock should not cause you any worry.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

我理解错误的起源，但不知道你可以将OUTPUT信号定义为reg，我认为物理信号必须是有线的。
关于此线程，将二进制计数器与时钟使能相结合看起来很有趣。
Sclkena
为什么4'b0110用于建立3Mhz时钟？
Sclkena是非阻塞的，因此在下一个时钟之前不会更新该值，当Sclkena被检查时，这将使值4'b0111，从而产生7Mhz时钟。
对于在正边缘敏感的3MHz时钟，您不希望初始值为4'b01111吗？
count_up和count_down的目的是什么？
如果我正确理解您的方法，这是生成1Hz和2Hz时钟的正确代码，并使两个LED相应地闪烁开/关吗？
当以这种方式执行always语句时（三个始终对同一信号敏感的语句），它们是并行还是顺序完成的？
模块核心（
输入CLK_50MHZ，// 50 MHz输入时钟
输出reg [1：0] led = 0）;
// LED总线输出驱动，ON = 1 / OFF = 0
reg ENABLE_CLK_1HZ = 0;
// 1HZ CLOCK ENABLE
reg ENABLE_CLK_2HZ = 0;
// 2HZ CLOCK ENABLE
reg [25：0] clk_counter = 0;
//时钟的二进制计数器
总是@（posedge CLK_50MHZ）clk_counter
我的目标是学习使用Verilog编程FPGA的基础知识。
此时40/60的工作周期对我的简单设计没有影响。
我将重新阅读我在Verilog上的书的前几章，我的下一个目标是在我的开发板上使用2x16 LCD显示屏。



以下为原文

I understood the genesis of the error but didn’t know you could define an OUTPUT signal as reg, I thought physical signals must be wire.

Using a binary counter in combination with clock enable looks interesting, regarding this thread.
 
Sclkena  <= (counter[3:0] == 4'h6);    // 3MHz  rate clock enable 
Why is 4'b0110 used to establish a 3Mhz clock? Sclkena is non-blocking, so the value won't be updated until the next clock, which would make the value 4'b0111 when Sclkena is checked thus generating a 7Mhz clock.  Wouldn't you want an initial value of 4'b01111 for a 3MHz clock that is sensitive on a positive edge?
 
What is the purpose of count_up and count_down?
 
If I understand your method correctly, is this is the correct code for generating a 1Hz and 2Hz clock and making two LEDs blink on/off accordingly?
 
Also when executing the always statements in this fashion (three always statements sensitive to the same signal), are they done in parallel or sequentially?
 
module Core(input CLK_50MHZ,   // 50 MHz input clockoutput reg [1:0] led = 0 );    // LED bus output drive, ON = 1 / OFF = 0reg ENABLE_CLK_1HZ = 0;// 1HZ CLOCK ENABLEreg ENABLE_CLK_2HZ = 0;// 2HZ CLOCK ENABLEreg [25:0] clk_counter = 0;  // binary counter for clockalways @(posedge CLK_50MHZ) clk_counter <= clk_counter + 1;// increment counteralways @(posedge CLK_50MHZ)beginENABLE_CLK_1HZ <= (clk_counter[25:0] == 50000000-1);// Enable 1Hz ClockENABLE_CLK_2HZ <= (clk_counter[24:0] == 25000000-1);// Enable 2Hz Clockendalways @(posedge CLK_50MHZ)beginif(ENABLE_CLK_1HZ)// Check if 1HZ clock is Enabledbeginled[0] <= ~led[0];// Invert LED[0] accordinglyendif(ENABLE_CLK_2HZ)// Check if 2Hz clock is enabledbeginled[1] <= ~led[1];// Invert LED[1] accordinglyendendendmodule 
My goal is to learn the basics of programming FPGA's using Verilog. At this point a 40/60 duty cycle would have no effect on my simple designs.

I'm going to re-read the first few chapters of the book I got on Verilog, my next goal is to use the 2x16 LCD display screen on my development board.

 

None


以下为原文

Why is 4'b0110 used to establish a 3Mhz clock?
 
The important requirement is that the clock enable is a single-cycle pulse which occurs once every 16 (50MHz) clock cycles.  A clock enable is not a clock.  REPEAT: a clock enable is NOT a CLOCK.
 
Example:
 

• Two 8-bit counters, both clocked with the same 50MHz clock.
  

• One counter is free-running.  It counts at a 50MHz frequency.
  

• The other other counter has a clock enable signal.  When the clock enable is '1', the counter clocks.  When the clock enable is '0' the counter maintains current value (state).
  

• The clock enable signal maintains a repeating sequence: 15 cycles of '0' followed by a single cycle of '1'.
  

• The second counter increments at 1/16 of the frequency of the free-running counter, or 50/16 MHz (roughly 3MHz)
  

• The frequency of bit[4] of the free-running counter matches the frequency of bit[0] of the second counter.
  

• The frequency of bits[7:5] of the free-running counter match the frequency of bits[4:1] (respectively) of the second counter.
  

• The clock enable is not a clock, so it does not appear in the process sensitivity list of the second counter.
  

• On the clock's positive edge, the current counter bit values and the clock enable are all evaluated to determine the process function -- and counter's next state.
  

Sclkena is non-blocking, so the value won't be updated until the next clock, which would make the value 4'b0111 when Sclkena is checked thus generating a 7Mhz clock.
 
Your description is incorrect.  The register delays the clock enable by a clock cycle, its frequency is not changed.  I do not understand your meaning for the phrase 'when Sclkena is checked'.
 
Wouldn't you want an initial value of 4'b01111 4'b1111 for a 3MHz clock that is sensitive on a positive edge?
 
Please explain why you think this.  Think in terms of hardware:  gates (or logic functions) and clocked registers.
 
What is the purpose of count_up and count_down?
 
You are referring to a design application in the linked thread which is a separate logic design problem.  We're discussing clock enables, let's pursue this one topic without the distraction of someone else's unrelated logic design problem.
 
If I understand your method correctly, is this is the a correct code for generating a 1Hz and 2Hz clock and making two LEDs blink on/off accordingly?
 
Nicely done, I approve, with one problem:  the counter needs to divide by 25,000,000(d) instead of divide by 2^25. Here is an important change:
 
Replace this
always @(posedge CLK_50MHZ) clk_counter <= clk_counter + 1;  // increment counter
 
always @(posedge CLK_50MHZ)
    begin
        ENABLE_CLK_1HZ <= (clk_counter[25:0] == 50000000-1);    // Enable 1Hz Clock
        ENABLE_CLK_2HZ <= (clk_counter[24:0] == 25000000-1);    // Enable 2Hz Clock
    end
 
with this:
always @(posedge CLK_50MHZ)
  if (clk_counter[24:0] == 25000000-1)  // divide by 25,000,000 to 2Hz, terminal count?
    begin
      clk_counter[24:0]  <= 0;  // wrap to 0

      clk_counter[25]  <= ~clk_counter[25];  // toggle bit[25] at 2Hz rate -- result is 1Hz
      ENABLE_CLK_2HZ <= 1; // Enable 2Hz Clock
      ENABLE_CLK_1HZ <= clk_counter[25]; // Enable 1Hz Clock

    end
  else  // in between 2Hz pulses
    begin
      clk_counter[24:0] <= clk_counter[24:0] + 1; // increment 2Hz counter
      ENABLE_CLK_2HZ <= 0; // Disable 2Hz Clock
      ENABLE_CLK_1HZ <= 0; // Disable 1Hz Clock

   end
 
Also when executing the always statements in this fashion (three always statements sensitive to the same signal), are they done in parallel or sequentially?
 
Software is executed sequentially, hardware operates in parallel.  We hardware snobs prefer the term 'concurrent'.  Sequenced logic in a single clocked process is called a state machine.  Any timing dependency between processes in hardware design must be explicit -- by design.
 
I'm going to re-read the first few chapters of the book I got on Verilog, my next goal is to use the 2x16 LCD display screen on my development board.

Don't lose sight of the fact that Verilog is a language.  It is a tool for describing hardware.  Learning hardware (and logic design) is not the same thing as learning Verilog.  Learning Verilog is not enough, you must also learn hardware.  In many ways, your life would be simpler if you learned hardware first, and then learned Verilog.  Always you must use the language correctly to generate the intended hardware design.  Understanding the desired end result is required to understand how Verilog is to be used.
 
-- Bob Elkind
SIGNATURE:
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Summary:
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2. Search the forums (and search the web) for similar topics.
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4. Do not post a new topic or question on someone else's thread, start a new thread!
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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“不要忽视Verilog是一种语言这一事实​​。它是一种描述硬件的工具。学习硬件（和逻辑设计）与学习Verilog不同。学习Verilog是不够的，你还必须学习硬件
在许多方面，如果您先学习硬件，然后学习Verilog，您的生活会更简单。您必须正确使用该语言来生成预期的硬件设计。了解所需的最终结果需要了解如何使用Verilog
“如果用VHDL取代Verilog，上述情况仍然适用。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

"Don't lose sight of the fact that Verilog is a language.  It is a tool for describing hardware.  Learning hardware (and logic design) is not the same thing as learning Verilog.  Learning Verilog is not enough, you must also learn hardware.  In many ways, your life would be simpler if you learned hardware first, and then learned Verilog.  Always you must use the language correctly to generate the intended hardware design.  Understanding the desired end result is required to understand how Verilog is to be used."

And the above remains true if you replace Verilog by VHDL.

------------------------------------------
"If it don't work in simulation, it won't work on the board."

重要的要求是时钟使能是单周期脉冲，每16（50MHz）个时钟周期发生一次。
时钟使能不是时钟。
REPEAT：时钟使能不是时钟。
我明白，这是一个50/50占空比的时钟，对吗？
模块内核（输入CLK_50MHZ，// 50 MHz输入时钟输出寄存器CLK_1MHZ = 0，// 1MHz时钟输出寄存器CLK_1MHZ_ENABLE = 0 // 1MHz时钟使能）;
reg [19：0] CLK_1MHZ_COUNTER = 0;
//时钟的二进制计数器总是@（posedge CLK_50MHZ）如果（CLK_1MHZ_COUNTER == 50  -  1）开始//开始// 50周期= 1MHz CLK_1MHZ_COUNTER
您的描述不正确。
寄存器将时钟使能延迟一个时钟周期，其频率不会改变。
我不明白你在“检查Sclkena时”这句话的含义。
这就是我的意思..谢谢你正确地说出来......
对于在正边缘敏感的3MHz时钟，您不希望初始值为4'b011114'b1111吗？
请解释你为什么这么想。
考虑硬件：门（或逻辑功能）和时钟寄存器。
第1部分：对于3MHz时钟，为什么使用4'h6的值，在启用时钟之前丢失两个时钟，经过仔细检查，我认为这是为了解释Sclkena和count_up / count_down是非阻塞的。
第2部分：4'h6的值是否会产生7Mhz时钟，而不是3Mhz时钟？
50MHz /（6 + 1）（下一个时钟）= 7.142MHz。
我不确定这是故意还是错误。
如果打算丢弃两个时钟，那么50MHz /（6 + 2）= 6.250MHz。
也许这是他们的实施所特有的。
很好，我赞成，有一个问题：计数器需要除以25,000,000（d）而不是除以2 ^ 24。
这是一个重要的变化：
谢谢，在使用我的逻辑分析仪后，我看到时间都搞砸了。
使用clk_counter [25]保持1Hz值的好主意，非常优雅，我会使用一个单独的计数器。
软件按顺序执行，硬件并行运行。
我们的硬件势利者喜欢“并发”一词。
单个时钟进程中的顺序逻辑称为状态机。
硬件设计过程之间的任何时序依赖性必须是明确的 - 通过设计
我无法理解定义。
我可以将状态机类似于中断处理程序，它是空闲的，直到外部事件发出信号吗？
如果在同一信号上触发了两个带有非阻塞代码的事件，那么它们是同时执行还是顺序执行？
不相关，但同样有趣，如何衡量绩效。
是否可以看到一段代码将执行多长时间。
不要忘记Verilog是一种语言的事实。
它是一种描述硬件的工具。
学习硬件（和逻辑设计）与学习Verilog不同。
学习Verilog是不够的，你还必须学习硬件。
在许多方面，如果你先学习硬件，然后学习Verilog，你的生活会更简单。
始终必须正确使用该语言来生成预期的硬件设计。
要了解Verilog的使用方法，需要了解所需的最终结果。
如果我得到一本关于这个主题的书，我应该先学习哪些科目？
逻辑设计？
你推荐哪些书？



以下为原文

The important requirement is that the clock enable is a single-cycle pulse which occurs once every 16 (50MHz) clock cycles.  A clock enable is not a clock.  REPEAT: a clock enable is NOT a CLOCK.
 
I understand, this is a clock with a 50/50 Duty Cycle, correct?
module Core(
   input CLK_50MHZ,                  // 50 MHz input clock
   output reg CLK_1MHZ = 0,         // 1MHz Clock
   output reg CLK_1MHZ_ENABLE = 0   // 1MHz Clock Enable
   );

   reg [19:0] CLK_1MHZ_COUNTER = 0;  // binary counter for clock
  
always @(posedge CLK_50MHZ)
   begin
      if(CLK_1MHZ_COUNTER == 50 - 1) begin   // 50 Cycles = 1MHz
         CLK_1MHZ_COUNTER <= 0;  // wrap to 0
         CLK_1MHZ_ENABLE <= 1;   // Enable 1MHz Clock
      end
      else begin
         CLK_1MHZ_COUNTER <= CLK_1MHZ_COUNTER + 1;   // Increment counter
         CLK_1MHZ_ENABLE <= 0;   // Disable 1Mhz Clock Enable
      end
   end
  
always @(posedge CLK_50MHZ)
   begin
      if(CLK_1MHZ_COUNTER < (50 / 2) ) begin   // 50% Duty Cycle, High
         CLK_1MHZ <= 1;
      end
      else begin   // 50% Duty Cycle, Low
         CLK_1MHZ <= 0;
      end
   end  
endmodule 
Your description is incorrect.  The register delays the clock enable by a clock cycle, its frequency is not changed.  I do not understand your meaning for the phrase 'when Sclkena is checked'.
 
That is what I meant to say.. thank you for phrasing it correctly...
 
 
Wouldn't you want an initial value of 4'b01111 4'b1111 for a 3MHz clock that is sensitive on a positive edge?
 
Please explain why you think this.  Think in terms of hardware:  gates (or logic functions) and clocked registers.

Part 1: For a 3MHz clock why are you using a value of 4'h6, you lose two clocks before the clock is enabled, upon closer inspection I think that was the intent to account for  Sclkena  and count_up/count_down being non-blocking.
 
Part 2: Would a value of 4'h6 generate a 7Mhz clock, not a 3Mhz clock?  50MHz / (6+1) (for the next clock)  = 7.142MHz.  I'm not sure if this is intentional or an error.  If the intention was to drop two clocks, then 50MHz / (6+2) = 6.250MHz.  Perhaps this is specific to their implementation.
 
Nicely done, I approve, with one problem:  the counter needs to divide by 25,000,000(d) instead of divide by 2^24. Here is an important change:
 
Thanks, after using my logic analyzer I saw the timings were all screwed up. Nice idea using clk_counter[25] to maintain the 1Hz value, very elegant, I would have used a separate counter.

Software is executed sequentially, hardware operates in parallel.  We hardware snobs prefer the term 'concurrent'.  Sequenced logic in a single clocked process is called a state machine.  Any timing dependency between processes in hardware design must be explicit -- by design
 
I’m having trouble understanding definitions. Can I make the analogy that a state machine is like an interrupt handler, It’s idle until an external event signals it?

If that’s the case if two events with non-blocking code are triggered on the same signal are they executed concurrently or sequentially? Unrelated, but equally interesting, how is performance gauged. Is it possible to see how long a block of code will execute.
 
Don't lose sight of the fact that Verilog is a language.  It is a tool for describing hardware.  Learning hardware (and logic design) is not the same thing as learning Verilog.  Learning Verilog is not enough, you must also learn hardware.  In many ways, your life would be simpler if you learned hardware first, and then learned Verilog.  Always you must use the language correctly to generate the intended hardware design.  Understanding the desired end result is required to understand how Verilog is to be used.

If I get a book on the subject, what is the subject(s) I should learn first? Logic Design? and what books do you recommend?

我明白，这[你发布的示例代码]是一个50/50占空比的时钟，对吗？
是。
没有模拟它，它看起来是正确的。
对于50分频，您可能不需要20位计数器。
你可以只用18位，或者甚至更少。
我无法理解定义。
我可以将状态机类似于中断处理程序，它是空闲的，直到外部事件发出信号吗？
状态机是一般逻辑构造，用于根据状态和状态之间的转换来描述顺序过程的结构。
中断处理程序是一个应用程序。
汽车是一种载体。
出租车是一辆汽车（或可能是面包车）出租，几乎总是染成黄色。
我并不是说听起来神秘，但你的比较远远不够。
你参加了学习课程吗？
如果不是，你应该是。
学习逻辑设计。
学习数字逻辑。
学习注册。
学习设计语言。
首先学习硬件然后学习工具（Verilog或VHDL）是有意义的。
如果在同一信号上触发了两个带有非阻塞代码的事件，那么它们是同时执行还是顺序执行？
不相关，但同样有趣，如何衡量绩效。
是否可以看到一段代码将执行多长时间。
这正是我担心的问题。
硬件是寄存器和门和线，而不是代码行或进程。
你的想法是设计Verilog，你应该设计硬件。
这就是为什么你需要注册学习课程，以便有人可以亲自向你解释这些东西，大量使用书籍，数据表，白板和示波器。
您认为您了解时钟启用的概念吗？
你还记得你对'slowclk'和BUFG以及'触发'信号的原始兴趣吗？
到目前为止，你在这个主题中学到了什么？
您如何向其他人解释“时钟启用”的概念？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
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以下为原文

I understand, this [the example code you posted] is a clock with a 50/50 Duty Cycle, correct?
 
Yes.  Without simulating it, it looks correct.  You probably don't need a 20-bit counter for divide-by-50.  You could get by with only 18 bits, or perhaps even fewer still.
 
I’m having trouble understanding definitions. Can I make the analogy that a state machine is like an interrupt handler, It’s idle until an external event signals it?
 
A state machine is a general logic construct, a structure for describing a sequential process in terms of states and transitions between states.  An interrupt handler is an application.  A car is a vehicle.  A taxicab is a car (or maybe a van) for hire, almost always coloured yellow.  I don't mean to sound mystical, but your comparison was way off the mark.
 
Are you enrolled in a study course?  If not, you should be.  Learn logic design.  Learn digital logic.  Learn registers.  Learn a design language.  It makes sense to learn the hardware first, and then learn the tool (Verilog or VHDL).
 
If that’s the case if two events with non-blocking code are triggered on the same signal are they executed concurrently or sequentially? Unrelated, but equally interesting, how is performance gauged. Is it possible to see how long a block of code will execute.
 
This is exactly the problem I feared.  Hardware is registers and gates and wires, not lines of code or processes.  Your mind is designing Verilog, you should be designing hardware.  This is why you need to be enrolled in study courses, so that someone can explain this stuff to you in person, making extensive use of books, datasheets, whiteboards, and oscilloscopes.
 
Do you think you understand the concept of clock enables?  Do you remember your original interest in 'slowclk' and BUFG and a 'triggerable' signal ?   What have you learned in this thread, so far?   How would you explain the concept of 'clock enables' to someone else?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

如果用VHDL替换Verilog，上述情况仍然适用。
如果用VHDL替换Verilog，我会感到困惑。
永远。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
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您的代码中的评论不需要支付额外费用。
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以下为原文

And the above remains true if you replace Verilog by VHDL.
 
If you replaced Verilog with VHDL, I would be confused.  Forever.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.