VHDL中的组件应该做什么

你好ev'body，我试图实现我找到的UDP / IP堆栈
Opencore Library，一切似乎都很好，但我找不到实体
Xilinx ISE 12.4支持（这是由11版IP核制作的），
所以我必须为这个实体编写代码。
原始代码是这样的
一：
- 合成translate_off
图书馆IEEE;
使用IEEE.STD_LOGIC_1164.ALL;
图书馆UNISIM;
使用UNISIM.VCOMPONENTS.ALL;
使用UNISIM.VPKG.ALL;
实体dist_mem_64x8是
港口 （
clk：在STD_LOGIC：='X';
a：在STD_LOGIC_VECTOR（5 downto 0）;
qspo：out STD_LOGIC_VECTOR（7 downto 0）
）;
结束dist_mem_64x8;
架构dist_mem_64x8的结构是
信号N0：STD_LOGIC;
信号N1：STD_LOGIC;
信号a_2：STD_LOGIC_VECTOR（5 downto 0）;
信号NlwRenamedSignal_qspo：STD_LOGIC_VECTOR（0 downto 0）;
开始
a_2（5）N1
）;
GND_1：GND
港口地图（
G => N0
）;
BU2_XST_GND：GND
港口地图（
G => NlwRenamedSignal_qspo（0）
）;
结束结构;
所以，我根本不明白这个组件应该做什么！
在异步模式下，6位数组中保存了6位输入。
有一个8位输出只能为他的输出的每个位[7 downto 0]获得一位信号[NlwRenamedSignal_qspo]
有一个名为BU2_XST_GND的模糊组件
有两个内部信号似乎未被使用[N0和N1]
所以，我不明白，这段代码应该做什么？
我怎么能简单地编写12.4 VHDL代码？
非常感谢！



以下为原文

Hello ev'body, I'm tried to implement an UDP/IP stack i found in Opencore Library, everything seemed to be fine but I found an entity not supported by Xilinx ISE 12.4 (this was made by the 11 version IP core), so I have to write the code for this entity. The original code is this one:

-- synthesis translate_offlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;library UNISIM;use UNISIM.VCOMPONENTS.ALL;use UNISIM.VPKG.ALL;entity dist_mem_64x8 is  port (    clk : in STD_LOGIC := 'X';     a : in STD_LOGIC_VECTOR ( 5 downto 0 );     qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )   );end dist_mem_64x8;architecture STRUCTURE of dist_mem_64x8 is  signal N0 : STD_LOGIC;   signal N1 : STD_LOGIC;   signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 );   signal NlwRenamedSignal_qspo : STD_LOGIC_VECTOR ( 0 downto 0 ); begin  a_2(5) <= a(5);  a_2(4) <= a(4);  a_2(3) <= a(3);  a_2(2) <= a(2);  a_2(1) <= a(1);  a_2(0) <= a(0);  qspo(7) <= NlwRenamedSignal_qspo(0);  qspo(6) <= NlwRenamedSignal_qspo(0);  qspo(5) <= NlwRenamedSignal_qspo(0);  qspo(4) <= NlwRenamedSignal_qspo(0);  qspo(3) <= NlwRenamedSignal_qspo(0);  qspo(2) <= NlwRenamedSignal_qspo(0);  qspo(1) <= NlwRenamedSignal_qspo(0);  qspo(0) <= NlwRenamedSignal_qspo(0);  VCC_0 : VCC    port map (      P => N1    );  GND_1 : GND    port map (      G => N0    );  BU2_XST_GND : GND    port map (      G => NlwRenamedSignal_qspo(0)    );end STRUCTURE;
So, I didn't understandd at all what this component is meant to do!

There's a 6 bit input saved in a 6 bit array in an asynchronous mode.
There's an 8 bit out that only gets an one bit signal [NlwRenamedSignal_qspo] for every bit [7 downto 0] of his output
There's an obscure component named BU2_XST_GND
There are two internal signals that seems to be unused [N0 and N1]

So, I didn't understand, what is this code supposed to do? and how could I simply write the 12.4 VHDL code counterpart?

Thanks a lot!