在电源循环期间，FPGA输出引脚是否会改变状态？

嗨阿南德，
你用什么样的界面来控制液晶显示器？
（VGA，DVI，HDMI）
数字接口可能需要正确设置和同步数据流。
也许这只适用于上电或重新编程后的设计，但不能在普通复位后或任何导致显示失败的情况下使用。
更多细节可能会有所帮助。
有一个很好的综合 
Eilert



以下为原文

Hi Anand,
what kind of interface are you using to controll the LCD? (VGA,DVI,HDMI)
The digital interfaces may need proper setup and synchronisation of the data streams.
Maybe this only works in your design after power up or reprogramming, but not after an ordinary reset or whatever causes the display to fail.
 
Some more details may be helpful.
 
Have a nice synthesis
  Eilert
 

您的问题描述有点令人困惑，因此我将重新发布您的帖子以验证正确的含义。
此外，您没有描述您正在使用的LCD类型。
我将假设这是一个板载字符LCD，而不是带有HDMI输入的21英寸平板显示器。
在我项目的每个电源循环期间，LCD首先启动，然后会有一个显示屏。
这是一个随机显示，还是一个编程的'welcome＆amp; amp;
准备'型显示器？
有时它不会来。
有时屏幕是空白的，有时显示是随机的？
每当我重新编程FPGA时，都会解决此问题。
没有循环供电，如果你重新启动FPGA，一切正常吗？
这听起来像FPGA初始化LCD之间的竞争条件，以及LCD上电并准备好进行FPGA初始化访问。
如果是这种情况，答案可能很简单：在初始化LCD的状态机中
A.添加一个足够长的固定延迟，以便LCD完成上电并准备就绪
要么
B.在开始LCD初始化序列之前添加逻辑以检查LCD的“就绪”状态。
由于电源回收，FPGA是否可以改变其输出引脚状态？
是的，当然输出引脚在电源循环期间和之后改变状态。
它们还会在程序配置序列期间更改状态，即使电源未循环也是如此。
这是你的意思吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
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以下为原文

Your problem description is a bit confusing, so I will rephrase your post to verify correct meaning.  Also, you don't describe what type of LCD you are using.  I will assume this is an onboard character LCD, rather than a 21-inch flat screen with HDMI input.

During every power cycle in my project LCD boots up first and there will be a display coming in it.

Is this a random display, or a programmed 'welcome & ready' type display?

Sometimes it doesn't comes.

Sometimes the screen is blank, or sometimes the display is random?

Whenever i reprogram the FPGA, this issue is resolved.

Without cycling power, if you 're-boot' the FPGA, everything is normal?
 
It sounds like a race condition between the FPGA initialising the LCD, and the LCD powering up and coming 'ready' for FPGA initialisation accesses.
 
If this is the case, the answer could be simple: In the state machine which initialises the LCD, either

A. add a fixed delay which is long enough for the LCD to complete power up and become ready

or

B. add logic to check LCD's 'ready' state before beginning LCD intialisation sequence.

Does FPGA can change its output pins state because of power recycling?

Yes, of course the output pins change state during and after power cycle.  They also change state during a program-configure sequence, even if power is not cycled.  Is this what you meant to ask?
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

嗨Eilert！
我使用的是VGA-TFT彩色液晶模块 -  NL6448BC20-18D。
问题：
只要打开电源，LCD显示屏就会出现。
它有时不会出现。
LCD显示器与FPGA无连接。
FPGA正在执行其他功能。
但我可以注意到，当LCD没有出现时，如果我重新编程FPGA，显示器就会正确显示。
LCD直接连接到微控制器 -  AT91SAM9263。
问候，
阿南德



以下为原文

Hi Eilert!
 
i am using VGA - TFT color LCD module - NL6448BC20-18D.
 
Problem:
 
LCD display should come up whenever the power is turned on. It doesnot come sometimes. LCD display has no connections to the FPGA. FPGA is performing other functionlaities. But i could notice whenever the LCD doesnot comes up and if i re-program the FPGA, the displays comes correctly. LCD is directly interfaced to Microcontroller - AT91SAM9263.
 
regards,
Anand
 
 

嗨Elkind！
您的问题描述有点令人困惑，因此我将重新发布您的帖子以验证正确的含义。
此外，您没有描述您正在使用的LCD类型。
我将假设这是一个板载字符LCD，而不是带有HDMI输入的21英寸平板显示器。
我使用的液晶显示器类型是VGA  -  TFT彩色液晶显示器 -  NL6448BC20-18D。
在我项目的每个电源循环期间，LCD首先启动，然后会有一个显示屏。
这是一个随机显示，还是一个编程的'welcome＆amp; amp;
准备'型显示器？
这是一个程序显示。
每次开机时都会显示欢迎信息。
有时它不会来。
有时屏幕是空白的，有时显示是随机的？
屏幕是空白的
每当我重新编程FPGA时，都会解决此问题。
没有循环供电，如果你重新启动FPGA，一切正常吗？
这听起来像FPGA初始化LCD之间的竞争条件，以及LCD上电并准备好进行FPGA初始化访问。
如果是这种情况，答案可能很简单：在初始化LCD的状态机中
A.添加一个足够长的固定延迟，以便LCD完成上电并准备就绪
要么
B.在开始LCD初始化序列之前添加逻辑以检查LCD的“就绪”状态。
这里的问题是FPGA与LCD无关。
LCD直接连接到微控制器。
FPGA仅用于执行其他一些功能。
由于电源回收，FPGA是否可以改变其输出引脚状态？
是的，当然输出引脚在电源循环期间和之后改变状态。
它们还会在程序配置序列期间更改状态，即使电源未循环也是如此。
这是你的意思吗？
但上电后，根据FPGA中实现的逻辑，输出将被设置。
这是我的观察。
为什么每次重新编程FPGA后，LCD显示器都与LCD接口无关。
问候，
阿南德



以下为原文

Hi Elkind!
 
Your problem description is a bit confusing, so I will rephrase your post to verify correct meaning.  Also, you don't describe what type of LCD you are using.  I will assume this is an onboard character LCD, rather than a 21-inch flat screen with HDMI input.

The type of LCD i am using is VGA - TFT color LCD display - NL6448BC20-18D.

During every power cycle in my project LCD boots up first and there will be a display coming in it.

Is this a random display, or a programmed 'welcome & ready' type display?
 
It is a programmed display. Everytime it displays a welcome message during power on.

Sometimes it doesn't comes.

Sometimes the screen is blank, or sometimes the display is random?
 
screen is blank

Whenever i reprogram the FPGA, this issue is resolved.

Without cycling power, if you 're-boot' the FPGA, everything is normal?
 
It sounds like a race condition between the FPGA initialising the LCD, and the LCD powering up and coming 'ready' for FPGA initialisation accesses.
 
If this is the case, the answer could be simple: In the state machine which initialises the LCD, either

A. add a fixed delay which is long enough for the LCD to complete power up and become ready

or

B. add logic to check LCD's 'ready' state before beginning LCD intialisation sequence.
 
Problem here is FPGA has no link with the LCD. LCD is directly connected to the Microcontroller. FPGA is only intended to perform some other functions.

Does FPGA can change its output pins state because of power recycling?

Yes, of course the output pins change state during and after power cycle.  They also change state during a program-configure sequence, even if power is not cycled.  Is this what you meant to ask?
 
But after power up, as per the logics realised in FPGA, the outputs will be set. This is my observation. Why everytime after reprogramming FPGA, LCD display comes when it has no relation to LCD interface.
 
regards,
Anand

 

显然，FPGA和LCD控制器芯片之间存在一些直接或间接的连接。
也许一些由FPGA产生的复位信号？
想到的唯一另一种可能性是，配置FPGA的过程会导致电源掉电，从而导致LCD控制器芯片复位。
这可能包括FPGA输出，它将FET或缓冲器驱动到错误状态，无意中使电源轨短路。
我确信可能还有其他直接或间接的交互路径，但只有董事会设计师才会知道它们可能是什么。
这可能不是解决问题最简单的问题。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Apparently there is some direct or indirect connection between the FPGA and the LCD controller chip.  Perhaps some reset signal generated by the FPGA?
 
The only other possibility that comes to mind is if the process of configuring the FPGA causes a power supply to dip, which in turn causes the LCD controller chip to reset.  This might include an FPGA output which drives a FET or buffer to the wrong state, inadvertently shorting a power supply rail.
 
I'm sure there might be other direct or indirect interaction paths, but only the board designer would have a clue as to what they might be.  This might not be the easiest problem to troubleshoot.
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

嗨阿南德，
我同意鲍勃的观点。
它不是直接的FPGA，而是在上电期间发生的一些副作用。
也许最好检查PCB和电容器上的电源线（更多，更少，其他值，其他位置）。
或者上电顺序有问题。
（所有电源电压与各自硬件部分连接的顺序。）控制器可能过早上电。
有一个很好的综合 
Eilert



以下为原文

Hi Anand,
I agree with Bob.
It's not directly the FPGA, but some side effect that happens during power up.
 
Maybe it's a good idea to check the supply wiring on the PCB and the Capacitors( more, less, other values, other placement).
Or there's something wrong with the power up sequence. (The order in which all the supply voltages are connected with their respective parts of hardware.) Maybe the controller is powered up too early.
 
Have a nice synthesis
  Eilert

我只想添加配置UG在第56页上说明可能适用的以下内容：
PROG_B激活期间的I / O行为建议在PROG_B处于活动状态（低电平）时忽略FPGA I / O的状态，直到FPGA重新配置完成为止。在PROG_B上检测到低电平脉冲后，I / O将被禁用
如果热插拔引脚被置为低，则为-ups。
热插拔引脚是Spartan-3系列中的HSWAP_EN，Spartan-3E系列中的HSWAP和扩展Spartan-3A系列中的PUDC_B。
无论是否需要终端，我们强烈建议从用户设计外部终止或驱动该引脚。
在PROG_B复位期间，不控制热插拔引脚可能导致未处理的I / O行为。指定为三态输出的引脚在PROG_B复位期间可能会出现高电平。
仅指定输入或输出的引脚不受影响。
如果设计无法容忍高脉冲三态输出引脚，请参见答案记录32653http：//www.xilinx.com/support/answers/32653.htm。



以下为原文

I just wanted to add that the config UG states on page 56 the following that might be applicable:
 
I/O Behavior during PROG_B Activation
It is recommended to ignore the state of the FPGA I/O while PROG_B is active (Low) until
the FPGA reconfiguration has completed.
Upon detection of a Low pulse on PROG_B, the I/Os will be disabled with pull-ups if the
hot swap pin is asserted Low. The hot swap pin is HSWAP_EN in the Spartan-3 family,
HSWAP in the Spartan-3E family, and PUDC_B in the Extended Spartan-3A family. It is
strongly recommended to externally terminate or drive this pin from the user design,
whether the termination is desired or not. Not controlling the hot swap pin can result in
unknown I/O behavior during PROG_B reset.
Pins specified as three-state outputs can glitch High during a PROG_B reset. Pins specified
as inputs or outputs only are not affected. If the design cannot tolerate a High pulse on
three-state output pins, see Answer Record 32653
http://www.xilinx.com/support/answers/32653.htm.

是的，就像格雷格所说的那样。
你的HSWAP引脚的连接是什么？
如果将其连接到低电平，则所有其他引脚将在配置期间上拉。
如果将此引脚拉高，则所有其他引脚在配置期间将浮动。



以下为原文

Yes, like Greg said.
What your HSWAP pin's connection?
If you connect it to low, all other pins will be pull-up during configuration.
if you pull this pin high, all other pins will be float during configuration.