fpga板上的输出引脚状态是什么

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See below
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如果引脚未连接到FPGA封装内部，请不要将其连接到PCB上的任何内容。如果您的设计未使用该引脚，也不要将其连接到PCB上的任何内容。
这些工具将在所有未使用的IO引脚上实例化内部上拉，您不必担心，我们会为您处理。
此外，对使用的任何输入引脚都没有任何伤害，并且悬空。
Noite确定您过去遇到的“噪音”问题，但FPGA设备设计用于处理所有IO引脚上的中间电压，这在许多应用中通常都存在。
取一些未使用的IO引脚，并将它们连接到接头或引脚字段非常有用，这样当您需要调试时，您可以轻松地将信号路由到这些备用引脚之一。
谢谢和RegardsBalkrishan -----------------------------------------------
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If the pin is unconnected internal to the FPGA package, do not connect it to anything on your pcb.

If the pin is unused by your design, also do not connect it to anything on your pcb.  The tools will instantiate an internal pullup on all unused IO pins, you do not have to worry about it, we take care of it for you.  Also, no harm is done to any input pin that is used, and left floating.  Noite sure what "noise" issues you have had in the past, but the FPGA device is designed to handle intermediate voltages on all IO pins asa that is normally present in many applications.

It is very useful to take a number of unused IO pins, and wire them to a header, or a pin field, so that when you need to debug, you may easily route a signal out to one of these spare pins.
Thanks and Regards
Balkrishan
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您说“未使用的输出端口”，但我认为您的确意味着未使用的I / O或引脚。
这是一个未定义为输入，输出或双向的引脚。
在这种情况下，引脚将处于三态或高阻态，但它可能还会附加弱PULLDOWN，因为这是未使用引脚的默认选项。
如果PCB具有弱的PULLUP电阻导致中间电压电平，则在某些情况下，这种弱PULLDOWN会产生问题。
您表示您正在使用Vivado 2014.4，并且此行为由以下XDC约束控制。
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] 
我建议覆盖默认的PULLDOWN并将值设置为PULLNONE。
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如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



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You said "unused output ports", but I think that you really mean an unused I/O or pin.  That is a pin that is not defined as an input, output or bi-dir.  In this case the pin will be tri-stated or high-Z, but it will likely also have a weak PULLDOWN attached to it as that is the default option for unused pins.  This weak PULLDOWN can create problems in some cases if the PCB has a weak PULLUP resistor resulting in an intermediate voltage level. 
 
You indicated that you are using Vivado 2014.4 and this behaviour is controlled by the following XDC constraint.
 
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]
 
I recommend overriding the default PULLDOWN and setting the value to PULLNONE.
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首先，我要感谢Balkrishan Ahirwal和mcgett的详细解释和帮助新手。
所以让我澄清一下问题。
以Nexys4 DDR板为例，FPGA芯片本身有物理硬件 - 物理硬件IO从Nexys4板（JA端口，VGA等）开始 - 端口在Verilog中声明并在xdc文件中定义
JB [1]以电路板为例＃IO_L1P_T0_AD0P_15 Sch = *** [1]，如果JB [1]在xdc文件中注释掉并且根本没有在Verilog中声明，我会看到什么电压？一个回复表示弱PULLDOWN而
另一个回复表明弱上拉。
[两位作者都获得了荣誉并在xilinx工作......]虽然我可以测量电压，但我有兴趣了解发生了什么。我假设使用set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]输出为hi-z
和undefined.Thanks



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Firstly I want to thank Balkrishan Ahirwal and mcgett for their detail explanations and helping out a newbie. So let me clarify my
question.  Using the Nexys4 DDR board as an example, there are
-physical pins on the FPGA chip itself
-physical hardware IO going off the Nexys4 board (JA ports, VGA, etc..)
-ports as declared in Verilog and defined in the xdc file

Using JB[1] the board as an example  #IO_L1P_T0_AD0P_15 Sch=***[1], what voltage would I see if JB[1] is commented out in the xdc file and not declared in Verilog at all?

One reply indicates a weak PULLDOWN while another reply indicates a weak pullup. [Both authors have received kudos and work at xilinx...] While I could measure the voltage, I am interested in understanding what's happening.

I assume that with

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

the output would be hi-z and undefined.

Thanks

@homgim
使用JB [1]电路板作为示例＃IO_L1P_T0_AD0P_15 Sch = *** [1]，如果JB [1]在xdc文件中被注释掉而未在Verilog中声明，我会看到什么电压？
- >正如@ mcgettt所说的那样依赖于你在生成比特流时使用的设置。
我假设使用set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]输出将是hi-z并且未定义。
- >对。
-Pratham ------------------------------------------------
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以下为原文

@homgim
 
Using JB[1] the board as an example  #IO_L1P_T0_AD0P_15 Sch=***[1], what voltage would I see if JB[1] is commented out in the xdc file and not declared in Verilog at all? --> As said by @mcgett this is dependepnt upon what settings you had used while generating bitstream.
 
I assume that with

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

the output would be hi-z and undefined.

 
--> Right.
-Pratham

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