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使用带有10ns SRAM的Spartan 3入门板,我有一个uP和一个视频控制器都运行在25mhz。
现在我正在使用块ram,但我想为SRAM制作一个控制器来仲裁这两个。 我的想法是控制器运行在100MHz,uP和视频在25MHz但180度。 离开phaze(我认为这就是你所说的)。 换句话说,uP时钟的上升沿将在视频时钟的下降沿同时发生。 这样我就可以将两者之间的RAM时间分开,这样当uP的时钟很高时,它会引起控制器的注意,而视频也是如此。 这样做的一个问题是我不确定控制器是否能以100MHz运行? 另外,根据我的阅读,该板上的Asych SRAM在时序方面非常挑剔。 我想我所问的是,在你看来,这是否是这个删除的可行解决方案? 我认为它会在理论上起作用,但是,很多事情都会在“理论上”起作用:) 谢谢, 凯文 以上来自于谷歌翻译 以下为原文 Using a Spartan 3 starter board with 10ns SRAM, I have a uP and a video controller both running at 25mhz. Right now I am using block ram but I want to make a controller for the SRAM to arbitrate the two. My thought was to have the controller run at 100MHz and the uP and video be at 25MHz but 180 deg. out of phaze (I think that is what you call it). In other words, the rising edge of the uP's clock will occur at the same time the falling edge of the video's clock. This would allow me to split up the RAM time between the two so that when the uP's clock is high, it has the controller's attention and the same for the video. One problem with this is that I am not sure that the controller can run at 100MHz??? Also, from what I have read, the Asych SRAM on this board is pretty picky when it comes to timing. I guess what I am asking is, in your opinions, is this a plausable solution to this delema? I think that it will work in theory but, alot of things will work "in theory" :) Thanks, Kevin |
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4个回答
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第一个想法 - 不要使用两个时钟。
以100MHz运行整个事件,并使用时钟使能两个每4个时钟周期启用25MHz位。 这让生活变得更加简单! 如果这不可行,建立一个到SRAM接口的FIFO接口(参见MPMC数据表中的一个例子(公认复杂!)如何做到这一点)。 然后,您的SRAM仲裁器可以在100MHz运行,并在备用(100MHz)时钟周期内接收uP和视频请求。 如果您尝试访问10ns * async * SRAM yu可能需要比100Mhz更快的时钟,以便控制器满足各种时序(并且可能使用时钟的两个边沿来处理某些信号)。 #是什么部分? 干杯, 马丁 Martin Thompsonmartin.j.thompson@trw.com http://www.conekt.co.uk/capabilities/electronic-hardware 以上来自于谷歌翻译 以下为原文 First idea - don't use two clocks. Run the whole thing at 100MHz, and use a clock enable two enable the 25MHz bit every 4 clock ticks. That makes life an awful lots simpler! If that's not feasible, build a FIFO interface to the SRAM interface (see the MPMC datasheet for an example (admittedly complex!) of how this is done). Your SRAM arbitrator can then run at 100MHz and pick up the uP and video requests on alternate (100MHz) clock ticks. If you are trying to access 10ns *async* SRAM yu might need a faster clock than 100Mhz for the controller to meet the various timings (and possibly use both edges of the clock for some signals). What part # is it? Cheers, Martin Martin Thompson martin.j.thompson@trw.com http://www.conekt.co.uk/capabilities/electronic-hardware |
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马丁,
SRAM是ISSI IS61LV25616AL(其中2个)。 输入时钟为50MHz,我得到25MHz这样: 当rising_edge(clk50MHz)时,clk25MHz不是clk25MHz; 我打算使用DCM将50MHz时钟提升到100.但是,现在我不确定。 谢谢, 凯文 以上来自于谷歌翻译 以下为原文 Martin, The SRAM is ISSI IS61LV25616AL (2 of 'em). The input clock is 50MHz and I derive the 25MHz like this: clk25MHz <= '0' when reset = '1' else not clk25MHz when rising_edge(clk50MHz); I was going to use a DCM to up the 50MHz clock to 100. But, now I am not sure about that. Thanks, Kevin |
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由于多种原因(时序分析,路由,时钟偏差等),设置这样的时钟是一个坏主意。
最好的方法是使用Martin建议的时钟启用方法。 例如 将50MHz时钟运行到所有FF,并使用T FF输出驱动CE,因此它们仅在慢速域上以25MHz启用。 还有其他方法,但我可能会尝试使这一方法先行。 BT 以上来自于谷歌翻译 以下为原文 Gating a clock like this is a bad idea for multiple reasons (timing analysis, routing, clock skew, etc.) The best approach is likely to use the clock enable approach Martin suggested. e.g. Run the 50MHz clock to all of the FFs and use the T FF output to drive the CEs so they are only enabled at 25MHz on the slow domain. There are other approaches but I would likely try to make that one work first. bt
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嗨,
正如蒂姆所说,产生这样的50%时钟会给你带来问题(现在,或者更可能是截止日期迫在眉睫:)运行50MHz时钟对你的逻辑要求不高,而备用时钟使能会解决仲裁问题 。 但是你不会从SRAM中获得全速率...... 干杯, 马丁 Martin Thompsonmartin.j.thompson@trw.com http://www.conekt.co.uk/capabilities/electronic-hardware 以上来自于谷歌翻译 以下为原文 Hi, As Tim says generating a 50% clock like that is going to cause you problems (either now, or more likely as a deadline looms :) Running a 50MHz clock is not too demanding for your logic and alternate clock enables will sort out the arbitration problem. But you won't get full rate out of the SRAM then... Cheers, Martin Martin Thompson martin.j.thompson@trw.com http://www.conekt.co.uk/capabilities/electronic-hardware |
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