[问答]

请问FPGA如何用verilog文件调用VHDL的程序并用modelsim仿真？

问答对人有帮助，内容完整，我也想知道答案 0 问题描述：DE10-nano板提供的工程顶层文件是verilog写的，自己编写了一个PID程序是用VHDL写的。现在要把PID放到工程中编译并使用modelsim仿真。如何操作？顶层文件DE10_Standard_GHRD.v： `define ENABLE_HPS //`define ENABLE_HSMC module DE10_Standard_GHRD( ///////// CLOCK ///////// input CLOCK2_50, input CLOCK3_50, input CLOCK4_50, input CLOCK_50, ///////// KEY ///////// input [ 3: 0] KEY, ...... wire hps_FPGA_reset_n; wire [3:0] fpga_debounced_buttons; wire [8:0] fpga_led_internal; wire [2:0] hps_reset_req; wire hps_cold_reset; wire hps_warm_reset; //ram_driver3_0 //input wire FCLK_5M; wire CHANNEL1_RAM_LOAD; wire [15:0] RAM_MS_A; wire [7:0] RAM_S_A; wire [7:0] RAM_MIN_A; wire [7:0] RAM_HOUR_A; //output wire [15:0] CHANNEL1_RAM_DATA; wire CHANNEL1_RAM1_WR_CLK; wire [7:0] CHANNEL1_RAM1_WR_ADDR; // connection of internal logics assign LEDR[9:1] = fpga_led_internal; assign stm_hw_events = {{4{1'b0}}, SW, fpga_led_internal, fpga_debounced_buttons}; assign fpga_clk_50=CLOCK_50; ...... //外加ram 1 RAM_2P RAM_2P_inst( .data ( CHANNEL1_RAM_DATA ), .wraddress ( CHANNEL1_RAM1_WR_ADDR ), .wrclock ( CHANNEL1_RAM1_WR_CLK ), .wren ( 1'b1 ), .rdaddress (ram_out_address), .rdclock (ram_out_rdclock), .q (ram_out_readdata) ); ...... reg [25:0] counter; reg led_level; always @(posedge fpga_clk_50 or negedge hps_fpga_reset_n) begin if(~hps_fpga_reset_n) begin counter<=0; led_level<=0; end else if(counter==24999999) begin counter<=0; led_level<=~led_level; end else counter<=counter+1'b1; end assign LEDR[0]=led_level; endmodule 复制代码代码太长，选择了关键部分截取。要调用的pid_controller.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity pid_controller is generic ( -- size of input and output data -- iDataWidith : integer range 8 to 32 := 8; -- proportionally gain -- iKP : integer range 0 to 7 := 3; -- 0 - /2, 1 - /4, 2 - /8, 3 - /16, 4 - /32, 5 - /64, 6 - /128, 7 - /256 -- integral gain -- iKI : integer range 0 to 7 := 2; -- 0 - /2, 1 - /4, 2 - /8, 3 - /16, 4 - /32, 5 - /64, 6 - /128, 7 - /256 -- differential gain -- iKD : integer range 0 to 7 := 2; -- 0 - /2, 1 - /4, 2 - /8, 3 - /16, 4 - /32, 5 - /64, 6 - /128, 7 - /256 -- master gain -- iKM : integer range 0 to 7 := 1; -- 0 - /1, 1 - /2, 2 - /4, 3 - /8 , 4 - /16, 5 - /32, 6 - /64 , 7 - /128 -- delay between samples of error -- iDelayD : integer range 1 to 16 := 10; -- 0 - controller use derivative of PATERN_I and PATERN_ESTIMATION_I, 1 - controller use error to work -- iWork : integer range 0 to 1 := 1 ); port ( CLK_I : in std_logic; RESET_I : in std_logic; -- error -- ERROR_I : in std_logic_vector(iDataWidith - 1 downto 0); -- threshold -- PATERN_I : in std_logic_vector(iDataWidith - 1 downto 0); -- current sample -- PATERN_ESTIMATION_I : in std_logic_vector(iDataWidith - 1 downto 0); -- correction -- CORRECT_O : out std_logic_vector(iDataWidith - 1 downto 0) ); end entity pid_controller; architecture rtl of pid_controller is --------------------------------------------------------------------------- -- purpose: make a std_logic_vector of size c_size and build from c_value -- function f_something ( constant c_size : integer; signal c_value : std_logic) return std_logic_vector is variable var_temp : std_logic_vector(c_size - 1 downto 0); begin -- function f_something -- var_temp := (others => c_value); return var_temp; end function f_something; ------------------------------------------------------------------------------- -- delay register -- type type_sr is array (0 to iDelayD - 1) of std_logic_vector(iDataWidith - 1 downto 0); ------------------------------------------------------------------------------- -- signals -- ------------------------------------------------------------------------------- signal v_error : std_logic_vector(iDataWidith - 1 downto 0); signal v_error_KM : std_logic_vector(iDataWidith - 1 downto 0); signal v_error_KP : std_logic_vector(iDataWidith - 1 downto 0); signal v_error_KD : std_logic_vector(iDataWidith - 1 downto 0); signal v_error_KI : std_logic_vector(iDataWidith - 1 downto 0); signal t_div_late : type_sr; signal v_div : std_logic_vector(iDataWidith - 1 downto 0); signal v_acu_earl : std_logic_vector(iDataWidith - 1 downto 0); signal v_acu : std_logic_vector(iDataWidith - 1 downto 0); signal v_sum : std_logic_vector(iDataWidith - 1 downto 0); begin -- architecture rtl -- -- choice source of input data -- v_error <= ERROR_I when iWork = 1 else conv_std_logic_vector(signed(PATERN_I) - signed(PATERN_ESTIMATION_I) , iDataWidith) when iWork = 0 else (others => '0'); -- master gain execute by shift of iKM bits to the right -- v_error_KM <= v_error when iKM = 0 else f_something(c_size => iKM , c_value => v_error(iDataWidith - 1)) & v_error(iDataWidith - 1 downto iKM) when iKM > 0 else (others => '0'); -- proportionally gain execute by shift of (iKP - 1) bits to the right -- v_error_KP <= f_something(c_size => iKP + 1 , c_value => v_error_KM(iDataWidith - 1)) & v_error_KM(iDataWidith - 1 downto iKP + 1); -- derivative gain execute by shift of (iKD - 1) bits to the right -- v_error_KD <= f_something(c_size => iKD + 1 , c_value => v_error_KM(iDataWidith - 1)) & v_error_KM(iDataWidith - 1 downto iKD + 1); -- integral gain execute by shift of (iKI + 1) bits to the right -- v_error_KI <= f_something(c_size => iKI + 1 , c_value => v_error_KM(iDataWidith - 1)) & v_error_KM(iDataWidith - 1 downto iKI + 1); DI00: process (CLK_I) is begin -- process DI00 if rising_edge(CLK_I) then -- synchronous reset -- if RESET_I = '1' then t_div_late <= (others => (others => '0')); v_div <= (others => '0'); v_acu <= (others => '0'); v_acu_earl <= (others => '0'); else -- delay register -- t_div_late <= v_error_KD & t_div_late(0 to iDelayD - 2); -- difference between samples -- v_div <= conv_std_logic_vector(signed(v_error_KD) - signed(t_div_late(iDelayD - 1)) , iDataWidith); -- integration of error -- v_acu <= conv_std_logic_vector(signed(v_error_KI) + signed(v_acu_earl) , iDataWidith); -- sum of N - 1 samples of error -- v_acu_earl <= v_acu; end if; end if; end process DI00; -- first stage of adder -- v_sum <= conv_std_logic_vector(signed(v_acu) + signed(v_div) , iDataWidith); -- correction and second stage of adder -- CORRECT_O <= conv_std_logic_vector(signed(v_error_KP) + signed(v_sum) , iDataWidith) when RESET_I = '0' else (others => '0'); end architecture rtl; 复制代码已经试过的方法：在顶层文件中用 `include 调用，但是两种语言语法有差别未成功。最终目的：在工程编译成功的前提下，实现在modelsim中的仿真（需能编写test bench文件）。 0
2019-4-29 11:31:11　　 1 评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × 刘英该类别下有 31 个回答。邀请回答 chenbingjy 该类别下有 27 个回答。邀请回答 yoonssica 该类别下有 22 个回答。邀请回答 houxiaoxiao 该类别下有 17 个回答。邀请回答小工兵该类别下有 16 个回答。邀请回答小萃米该类别下有 16 个回答。邀请回答 Elecfans管家该类别下有 15 个回答。邀请回答薄迪该类别下有 14 个回答。邀请回答我爱妖妖该类别下有 14 个回答。邀请回答言尽于此33 该类别下有 14 个回答。邀请回答 hxing 该类别下有 13 个回答。邀请回答那些年儿ing 该类别下有 13 个回答。邀请回答平漂流该类别下有 13 个回答。邀请回答小麦地该类别下有 12 个回答。邀请回答科比如我该类别下有 12 个回答。邀请回答倪love 该类别下有 12 个回答。邀请回答 xiekaboy 该类别下有 12 个回答。邀请回答 1653344032.827400 该类别下有 12 个回答。邀请回答 2013crazy 该类别下有 11 个回答。邀请回答英雄孤寂该类别下有 11 个回答。邀请回答举报仼葭浚相关推荐 • FPGA入门之ModelSim的安装步骤 5631 • 关于Modelsim的使用方法请教 5856 • 关于modelsim和matlab协仿真的问题，用的是verilog语言。。。。 2080 • 怎样在Verilog写的testbench测试VHDL模块?? 7377 • ModelSim IntelFPGA中是否提供VHDL源代码模板？ 1769 • 请问我的Quartus在编译后自动调用ModelSim 就会仿真失败 6171 • 用VHDL调用verilog时遇到一个神奇的问题 4096 • Modelsim如何仿真一个工程文件 4045 • 用quartusii 9.1 生成的vht文件，testbench等问题 8475 • ModelSim仿真出现near timescal！！！ 4049 1 条评论仼葭浚 2019-4-29 12:27 别的方法也可以，只要最终实现目的即可。赞回复举报 2个回答