BRAM，DRAM和DMA之间的区别是什么

一切都完全不同
看看谷歌或类似的
DMA。
直接内存访问。
移动内存块的方法
DRAM：动态随机存取存储器：读写存储器，但需要定期刷新，在此期间无法访问正在刷新的单元。
BRA：Sram内置于FPGA中。
希望有助于家庭工作。



以下为原文

all totally different
 
look on gogle or similar
 
 
DMA . Direct memory Access. way to move lumps of memory around 
 
 
DRAM : Dynamic random Access Memory :  Read and write memory, but needs to be regularly refreshed during which you can't access the cells being refreshed.
 
BRA : Sram built into the FPGA.
 
Hope that helped on home work.
 
 
 

@drjohnsmith感谢您立即回复。
我的理解是正确的，BRAM位于PL侧（FPGA），而DRAM位于PS侧（ARM主机）？
哪一个使用效率最高？
谢谢。



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@drjohnsmith

Thanks for the immediate response. Is my understanding  is correct that BRAM is located in the PL side (FPGA) while the DRAM is located in the PS side (ARM host)? And which one is the most efficient to used?


Thanks.

在这种情况下，BRAM位于PL逻辑中。
DRAM根本不在零件上 - 它在电路板上是外部的。
DRAM的INTERFACE在PS上。
您需要通过“最有效”来定义您的意思。
上述每个存储器具有不同的成本/益处/特征。
没有一般的“这个更好”。
问候，
标记



以下为原文

 
In this context, the BRAM is located in the PL logic.
The DRAM is NOT located on the part at all - it's external on the board.  The INTERFACE to the DRAM is on the PS.
 
You'll need to define what you mean by "most efficient".  Each of the above memories has different costs / benefits / features.  There's no general "this one is better".
 
Regards,
 
Mark

@glennparaiso
假设你有一群二十人在看有趣的蚱蜢，并试图记住每个人的样子。
该组还有一个（共享）数码相机，可用于拍摄蚱蜢的照片。
当人们记住每只蚱蜢的样子时，你会得到BRAM。
这是非常快的（它发生的速度就像你能看到和记住的那样快），并且没有拥塞（每个人都可以单独看到和记住蚱蜢）。
但是，每个人记忆的数量都有很低的限制。
即使能够完美地记住一只蚱蜢的形状/颜色也会令人印象深刻;
能做十到二十次会很棒。
DRAM是你用数码相机得到的。
它慢得多，一次只能有一个人使用它。
但是，你可以完美地“记住”数百只蚱蜢的形状/颜色。
数码相机的优点还在于，由于它是共享的，您可以向其他人展示您看到的蚱蜢。
您只需为作业选择正确的设备即可。
Block RAM具有高带宽和极低延迟，大多数芯片上都有数百个Block RAM（因此每个设计模块都可以使用一些）。
然而，它非常小 - 存储单个640x480彩色图像将使用比许多较小芯片可用的更多的块RAM。
片外RAM（DRAM）具有高带宽，但必须在所有块之间共享该带宽。
延迟很高，如果有太多的块试图立即访问RAM，则延迟可能非常高。
另一方面，找到一块装有1GB DDR3 RAM的电路板并不常见 - 足以容纳数千张图像。
由于DRAM是共享的，因此您可以轻松地使用它在块之间传输数据（这是在PL和PS之间获取数据的主要方式之一）。



以下为原文

@glennparaiso
 
Suppose you've got a group of twenty people looking at interesting grasshoppers, and trying to remember the what each one looks like. The group also has a single (shared) digital camera that can be used to take photos of grasshoppers.
 
BRAM is what you get when people just remember what each grasshopper looks like. It's very fast (it happens as quickly as you can see and remember something), and there's no congestion (everyone can see and remember grasshoppers individually). However, there's a pretty low limit on how much each person can remember. Even being able to remember the shape/colour of one grasshopper perfectly would be impressive; being able to do ten or twenty would be amazing.
 
DRAM is what you get with the digital camera. It's much slower, and only one person can use it at a time. However, you can "remember" the shape/colour of hundreds of grasshoppers perfectly. The digital camera also has the advantage that, because it's shared, you can show everyone else what grasshoppers you saw.
 
 
You simply have to select the right device for the job.
 
Block RAM has high bandwidth and extremely low latency, and most chips have hundreds of block RAMs on them (so each design module can use a few). However, it's very small - storing a single 640x480 colour image will use more block RAMs than many of the smaller chips have available.
 
Off-chip RAM (DRAM) has high bandwidth, but that bandwidth has to be shared between all the blocks. Latency is high, and can be extremely high if too many blocks are trying to access the RAM at once. On the other hand, it's not at all unusual to find a board with 1GB of DDR3 RAM fitted - enough for thousands of images. Because the DRAM is shared, you can easily use it to transfer data between blocks (and this is one of the main ways of getting data between the PL and PS).
 

非常感谢u4223374，详细解释。
你能否确认我是否理解你：
1. BRAM可以逐个分配，每个都有自己的地址和数据线，可以读/写， 
所有在相同的时钟周期同步;
但BRAM的总量很小;
2. DRAM只有一组地址和数据线，只能在不同的模块/设备之间进行分时; 
但DRAM要大得多。
关于延迟，DRAM通常可以比PL运行得快得多，所以如果DRAM连接的话
到PL，PL为200 MHz，DRAM内部频率为1 GHz，DRAM看起来像PL一样
不是太慢了？
我的问题是：如果我想从PL直接写入PL端DRAM，
DRAM有没有机会跟上？
再次感谢您，最诚挚的问候，



以下为原文

Thank you very much u4223374, for the detailed explanation.
 
Could you please confirm whether I understood you correctly:
1. BRAM can be allocated piece by piece, each has its own address and data lines and can be read/written to,
    all in the same clock cycles synchronously; but the total amount of BRAM is small;
2. DRAM only has one set of address and data lines, can only be time-shared between different modules/devices;
    but the DRAM is much larger.
 
Regarding the latency, is it true that the DRAM usually can run much faster than the PL, so if the DRAM is connected
to the PL, PL is at 200 MHz and the DRAM internal frequency is 1 GHz, the DRAM would appear to the PL as
not too slow?  My question really is: if I would like to continuously write from the PL directly to the PL-side DRAM,
is there any chance the DRAM can keep up?
 
Thank you again, best regards,

不
DRAM连接到PS侧，它的臂如何启动/运行。
DRAM也可以连接到PL侧，
BRAM是基于SRAM的，DRAM是基于DRAM的， 
（静态v动态）



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nope
 
DRAM is connected to the PS side, its how the arm boots  / runs.
 
DRAM CAN also be connected to the PL side, 
 
BRAM is SRAM based, DRAM is DRAM based,  
   ( Static v Dynamic )