Virtex 6到Artix 7的迁移

@ rakeshm55，
在这样的场景中，该工具正在努力满足时序，这导致更长的运行时间。
我建议你检查并比较设计的日志文件与Virtex 6和Artix 7。
Artix 7设计中的任何信息/警告/严重警告消息都应该提供线索
另请检查以下迁移用户指南是否有用。
http://www.xilinx.com/support/documentation/sw_manuals/ug429_7Series_Migration.pdf
--Syed
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以下为原文

@rakeshm55,
 
In such scenerio the tool is trying hard to meet timing which is resulting in longer runtime.
I would suggest you to check and compare both the log files of design with Virtex 6 and Artix 7.
 
Any info/warning/Critical warning message in Artix 7 design should give a clue
 
Also check if the below migration User guide is helpful.
http://www.xilinx.com/support/documentation/sw_manuals/ug429_7Series_Migration.pdf
 
--Syed
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您在设计中使用的核心和原语是什么。您可以共享测试用例来重现此问题
谢谢和RegardsBalkrishan -----------------------------------------------
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以下为原文

what are the core and primitives you are using in the design .You may share the test case to reproduce this issueThanks and Regards
Balkrishan
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-----你在设计中使用的核心和原语是什么？
主要IP设计使用系统生成器
VHDL中使用的核心包括（coregen FIFO＆amp; coregenDPRAM＆amp; ILA＆amp; ICON）.....
您可以分享测试用例来重现这个问题---如何分享？
我应该分享什么？



以下为原文

-----what are the core and primitives you are using in the design??
 
Major IP design uses System generator
Cores used in VHDL include (coregen FIFO &  coregenDPRAM & ILA & ICON ).....
 
You may share the test case to reproduce this issue--- How to share it ?? what should i share??
 
 
 
 

你可以附上论坛帖子的测试用例
谢谢和RegardsBalkrishan -----------------------------------------------
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以下为原文

you can attach test case with forums postThanks and Regards
Balkrishan
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请告诉我这是否打算
red_flip.syr 781 KB
red_flip.twr 675 KB
red_flip.twx 762 KB
red_flip_map.mrp 3548 KB



以下为原文

please let me whether this is what to intend
            red_flip.syr ‏781 KB                red_flip.twr ‏675 KB                red_flip.twx ‏762 KB                red_flip_map.mrp ‏3548 KB

我想知道你在sysen flow1中使用的编译目标。
使用生成的HDL2在sysgen中生成HDL并在Vivado中运行时序。
在sysgen中直接运行运行时序
谢谢和RegardsBalkrishan -----------------------------------------------
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以下为原文

I would like to know which compilation target you are using in sysen flow

1. Generate HDL in sysgen and running timing in Vivado with generated HDL

2. Directly running running timing in sysgenThanks and Regards
Balkrishan
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我正在使用ISE 14.7 ....＆amp;
Target Target芯片组是Artix 7 XC7A200T-FBG676 .....我最早会提供的其他细节



以下为原文

I am using ISE 14.7....&
Target Target chipset is Artix 7  XC7A200T-FBG676..... Other details I will provide at the earliest
 
 

在sysge中运行计时时遇到了这个错误
“” ＃----------------------------------------------＃
#starting program_par_trce＃trce -v 150 -intstyle xflow -xml phy_wb_hdr_wf_cw.twx -o phy_wb_hdr_wf_cw.twrphy_wb_hdr_wf_cw.ncd phy_wb_hdr_wf_cw.pcf＃----------------------
------------------------＃ERROR：TimingToolsC：14  - 无法访问设计文件：phy_wb_hdr_wf_cw.ncdxflow完成！“”



以下为原文

While running timing in sysge I met with this error
 
""#----------------------------------------------#

# Starting program post_par_trce

# trce -v 150 -intstyle xflow -xml phy_wb_hdr_wf_cw.twx -o phy_wb_hdr_wf_cw.twr

phy_wb_hdr_wf_cw.ncd phy_wb_hdr_wf_cw.pcf

#----------------------------------------------#

ERROR:TimingToolsC:14 - Unable to access design file: phy_wb_hdr_wf_cw.ncd

xflow done!""
 

我无法在sysgen上运行时序分析器.....但我可以在集成文件（wrapper + sysgen）上运行时序分析器工具并解决sysgen中的设置时序错误
现在，当我运行时序分析器时，我得到保持时间错误......这不会出现在sygen设计文件中，而是出现在包装器（* .vhd）....即使消除了一个路径后，错误也会再次出现在下一个路径中。
...我附上结果.....这是后映射时序分析器结果....
怎么解决这个???
我附加了为映射选择的设置的屏幕截图...这与默认设置不同...
分析1.twx 309 KB



以下为原文

I could not succeed in running timing analyzer on sysgen..... But I could run timing analyzer tool on the integrated file (wrapper + sysgen) and  resolve setup timing errors in sysgen
 
 Now when I run the timing analyzer , I get hold time errors.....this does not appear in sygen design files but on wrapper (*.vhd).... even after eliminating one path the error reappears in  next path.... I am attaching the result.....this is post map timing analyzer result....
 
How to resolve this ???
 
I am attaching the screen shot of settings chosen for mapping... this deviates from the default settings...
            Analysis 1.twx ‏309 KB