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我使用32位从FIFO同步模式。我需要发8KB的数据到PC,我把它们分成16包,每包128个模块(512b),在每个数据包的一端,有一个packet_end信号。设置1024b是端点缓冲区大小和我保持监测全旗以确保没有溢出。然而,我不能在USB控制中心接收整个8KB的数据。而我只得到了2342 ~23 96B,每次都不同。有人能告诉我什么是合适的问题吗?我相信FPGA已经将数据写入CYUSB3014芯片的特点,并且没有溢出。
以上来自于百度翻译 以下为原文 I am using 32bits slave FIFO sychronous mode. I need to send 8KB data to PC, and I divided them into 16 packets, each packet is 128*32bits (512B), at the end of each packet, there is a packet_end signal. The endpoint buffer size was set to 1024B and I keep monitoring the full flag to make sure there is no overflow. However, I can not receive the whole 8KB data in the USB control center. Instead I only got 2342~2396B, each time different. Can anybody tell me what may be the proper problem? I am sure FPGA has write the data into CYUSB3014, and there is no overflow. |
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9个回答
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FX3将数据分割成最大分组大小的分组并将其发送到主机。您不必在每512个结束时声明PayTeToEnter。
对于丢失的数据,你看到丢失的数据,即第一个2K是接收模式,512接受等交替的包吗? 当做, 阿南德 以上来自于百度翻译 以下为原文 FX3 will split the data to packets of maximum packet size and send it to the host. You don't have to assert the packet_end at the end of each 512. With regards to missing data, do you see a pattern in the missing data i.e. first 2k is being received, alternate packets of 512 being received etc etc? Regards, Anand |
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是的,我已经检查了数据模式。第一个512B被正确接收,然后丢失了22B,然后接收240B,然后丢失了22B,然后……这就是法律。你能看出原因吗?
以上来自于百度翻译 以下为原文 Yes, I have checked the data pattern. The first 512B was received correctly, then 272B missing, then 240B received, then 272B missing, then ...... That's the law. Can you see the reason? |
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否则,我试着给每个512b没有packet_end,但是USB控制中心没有收到!为什么?
以上来自于百度翻译 以下为原文 Otherwise, I tried sending each 512B without packet_end, but USB Control center received nothing! why? |
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为了正确地在缓冲器完全停止也在分组结束模式下,您必须监视部分全标志(以移除3时钟延迟)和正常完整标志。如果所有缓冲器都满,则将带有分组结束的短数据包发送到从FIFO不设置部分满标志。此情况仅由正常满标志进行。也许这是你的问题。
以上来自于百度翻译 以下为原文 For correct stopping at buffer full also in packet end mode, you have to monitor the partial full flag (to remove the 3 clock latency) and also the normal full flag. Wrting short packets with packet end to the slave fifo does not set the partial full flag if all buffers are full. This case is only hadled by the normal full flag. Maybe this is your problem. |
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如何同时使用正常满旗和分旗?现在我使用FraviA作为读取线程空标志,而FraveB作为写线程满标志。在数据传输期间,我一直在监视全标志,即使考虑到3个时钟周期的延迟,我也不应该丢失这么多的数据。
以上来自于百度翻译 以下为原文 How to use both normal full flag and partial flag at the same time? Now I am using flag_a as read thread empty flag, and flag_b as write thread full flag. During the data transfering, I was keep monitoring the full flag, even if considering the 3 clock cycle latency, I shouldn't lose so much data. |
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一般来说,如果我想把海量数据从FX3传送到PC,我应该如何组织我的数据包?例如,我使用线程0作为写入通道,并将套接字缓冲区大小设置为2048字节。每次我用PockEtEnEd信号将1024B数据写入缓冲区。这个方法行吗?还是有一个使用奴隶FIFO传输海量数据的最佳策略?
以上来自于百度翻译 以下为原文 Generally if I want to transfer mass data from FX3 to PC, how should I organize my data packets? For example, I used thread 0 as the write channel and set the socket buffer size to 2048B. Each time I write 1024B data into the buffer with a packet_end signal. Is this method alright? Or there is a best strategy to use slave FIFO to transfer mass data? |
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如果你看正常的完整标志,问题应该是另一个问题。我们的系统从硬件请求数据,并且可以在读请求命令中设置数据包结束。因此,我们能够尽可能大的传输数据块,并将数据包端设置为数据块的逻辑端。不需要用分组结束标记每个分组。如果你不能把数据包的末尾设置在一个完整的数据包的最后一个字上,那么数据就会丢失。所以,我设置的数据包结束总是一些循环后的最后一个字。在主机软件中可能有一个零长度的分组,但这是没有问题的,在主机软件中的协议解码器可以管理这个。顺便说一下:我们使用WiUSB驱动程序。目前,我运行了一个基于DVK的硬件连接到我们的“旧”硬件取代FX2直接。在主机软件中没有变化。我只需要稍微改变一下FPGA设计。它运行稳定的时间与不同的数据块长度。
以上来自于百度翻译 以下为原文 If you watch the normal full flag the problem schould be another. Our system requests data from the hardware and can set the packet end in the read request command. So we are able to transfer data blocks as large as possible and set the packet end to the logical end of a data block. There is no need to mark every packet with packet end. AFAIK you cannot set the packet end on the last word of a full packet, there will be data loss. So I set the packet end always some cycles after the last word. In the host software there may be a zero length packet, but this is no problem, the protocol decoder in the host software can manage this. By the way: we use WinUSB driver. At the moment I run a hardware based on the DVK connected to our "old" hardware replacing the FX2 directly. There was no change needed in the host software. I only had to change the FPGA design slightly. It runs stable for hours with different data block lengths. |
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嗨,Chris R.,我想知道你如何避免3秒的潜伏期。
你能给我更多的细节来配置关于PARTILL标志的GPIF吗? 以上来自于百度翻译 以下为原文 Hi Chris R. ,I want to know you how to avoid the 3 clock latency Can you give me more details to configure the GPIF about partril flag. |
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Jon:我在另一个论坛帖子中描述了这一点。
数据丢失:今天我做了SOM测试,发现FX2和FX3之间有很大的差异。如果我用最大的数据包大小填充缓冲区,如果我从设备请求精确的大小,我只能得到数据。如果我要求更多的数据,FX3挂起,必须重新设置。在FX2中,这是可能的,使用分组结束后的最后一个字和启用ZLPS的一些周期。同样的技术在FX3上不能正常工作。 以上来自于百度翻译 以下为原文 jogn: I described this in another forum thread here. To the data loss: Today I made som tests and figured out, that there is a big difference between FX2 and FX3. If I fill the buffer with exact the max. packet size, I only can get the data if I request the exact size from the device. If I request more data, the FX3 hangs and has to be reseted. In the FX2 this was possible using packet end some cycles after the last word and enabling ZLPs. The same technique does not work correctly on FX3. |
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