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大家好。
我有一个我为KC705开发板定制的设计。 我的设计100%工作。 但是我将这个基础设计提供给我的客户,他的客户也购买了KC705并且设备没有在他的电路板上工作。 所以他们给我发了他们的电路板,我一直在比较它们 - 它们具有完全相同的配置。 经过多次故障排除后,我已经达到了这样的程度,即我所设置的MMCM中的一个正在通过衍生时钟,但是没有锁定他的电路板。 有关如何进一步排除故障的任何想法? 我已经尝试将复位反转到MMCM,我已经尝试将它们从上电设置为静态。 没有什么能让MMCM锁定在这一块板上,但它对我的锁定很好。 这是我的实例,所以你可以看到我为它设置的频率: inst_MIG_CLK:K7_CLK_GEN端口映射(clk_in1_p => VID_CLK_P, - 200MHz P clk_in1_n => VID_CLK_N, - 200MHz N CLK_OUT1 => user_sysclk, - 333 MHz CLK_OUT2 => user_refclk, - 200 MHz MIG锁定参考=> locked_mig_clk - -resetn =>'0'); P和N进入user_sma_clk P / N引脚K25和L25,FWIW。 如果有人有任何故障排除线索或之前已经解决了这个问题,请提前感谢。 再次 - 在一块板上工作,而不是在客户上工作。 哦,我尝试将MMCM移动到另一个实例并且每个标志都爆炸了。 还尝试将模块更改为同一个磁贴站点的PLL,它也做同样的事情......没有锁定。 以上来自于谷歌翻译 以下为原文 Hi, all. I have a design that I've customized for the KC705 dev board. My design is working 100%. But I deliver this base design to my customer who also has purchased a KC705 and the desing is not working on his board. So they sent me their board, and I have been comparing them side by side - they have the exact same configuration. After much troubleshooting, I have gotten to the point where one of the MMCM's I desinged in is passing through the derived clocks, but is not locking on his board. Any ideas on how to further troubleshoot this? I have tried inverting resets to the MMCM, I have tried setting them static from power-up. Nothing gets the MMCM to lock on this one board, but it locks just fine on mine. Here is my instantiation, so you can see the frequencies I have set it up for: inst_MIG_CLK: K7_CLK_GEN port map ( clk_in1_p => VID_CLK_P, --200MHz P clk_in1_n => VID_CLK_N, --200MHz N CLK_OUT1 => user_sysclk, --333 MHz CLK_OUT2 => user_refclk, --200 MHz reference for MIG locked => locked_mig_clk --resetn => '0' ); The P and N are coming in on the user_sma_clk P/N pins K25 and L25, FWIW. thanks in advance if anyone has any troubleshooting clues or has solved this before. Again - works on one board, not on the customers. Oh, and I tried moving the MMCM to another instance and everythign blew up. Also tried changing the module to a PLL for the same tile site and it does the same thing....no lock. |
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6个回答
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嗨,
为什么不直接将时钟转发到某个IO并检查客户板上的输出。 我想确保振荡器提供时钟输出。 另外,请根据此调试清单第1点和第2点检查客户板的运行状况-http://www.xilinx.com/support/answers/50079.html 谢谢,AnirudhPS:请将此标记作为答案,以防它有助于解决您的问题。如果帖子引导您找到解决方案,请给予赞誉。 以上来自于谷歌翻译 以下为原文 Hi, Why dont you forward the clock to some IO directly and check the output on the customer board. I want to make sure the oscillator is giving the clock output. Also please check the customers board health as per this debug checklist point 1 and 2 - http://www.xilinx.com/support/answers/50079.html Thanks, Anirudh PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution. |
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看起来您没有将重置输入连接到MMCM。
您是如何在组件实例化时连接重置的。 在下面的链接中有关于计时调试的指南.http://www.xilinx.com/support/troubleshoot/clocking_debug.htm同样的指南也可以跟随7系列。 检查状态信号CLKINSTOPPED或CLKFBSTOPPED。 此外,将复位输入转到VIO并检查应用手动复位是否有帮助。 -------------------------------------------------- ----------------------------别忘了回复,给予kudo并接受为解决方案--------- -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 It looks like you are not connecting reset input to MMCM. How did you connect the reset at the component instantiation. There are guidelines about clocking debug at the link below. http://www.xilinx.com/support/troubleshoot/clocking_debug.htm Similar guidelines can be followed with 7-series also. Check the status signals CLKINSTOPPED or CLKFBSTOPPED. Also, take the reset input to a VIO and check if applying a manual reset helps. ------------------------------------------------------------------------------ Don't forget to reply, give kudo and accept as solution ------------------------------------------------------------------------------ |
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我认为,他们正在推出适当的PLL导出频率。
以上来自于谷歌翻译 以下为原文 I dd that, and they are coming out the as the proper PLL derived frequencies. |
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Venkat,是的,我意识到在我发布之后,谢谢。
当我改变感觉时,重置变为重置。 我玩那个,仍然没有锁定。 以上来自于谷歌翻译 以下为原文 Venkat, yes I realized that after I posted that, thanks. The resetn changed to reset when I changed the sense. I played with that, and still no lock. |
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我刚注意到我的客户的主板是V1.2,我们的是V1.1。
我没有找到Rev 1.2原理图,但我确实找到了三角洲的AR。 http://www.xilinx.com/support/answers/59751.html ************************* 新行为:所以我最终通过将该时钟巧妙地操纵到该板上可用的不同差分时钟引脚来解决问题。 我所要做的就是改变一组引脚位置并瞧! 它适用于客户卡。 现在,我让我的技术人员修改我们的电路板以获得相同的模块,并使用新的引脚布局加载设计的新旋转。 坏消息,现在我们的卡不起作用。 我们是否确定在1.1和1.2之间的董事会修订中没有更多的进展? Venkat或任何人我们如何验证这一点? 以上来自于谷歌翻译 以下为原文 I just noticed my customers' board is a V1.2 and ours is a V1.1. I found no Rev 1.2 schematic but I did find an AR for the delta. http://www.xilinx.com/support/answers/59751.html ************************* New behaviour: So I ultimately fixed the problem by some crafty maneuvering of that clock to different differential clock pins that were available on that board. All I had to do was change one set of pin locations and voila! It works on the customer card. Now, I had my tech modify our board for the same mods, and loaded the new spin of the design with the new pin layout. Bad news, now our card doesn't work. Are we sure there wasn't more going on in the board revision between 1.1 and 1.2? Venkat or anyone how can we verify this? |
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嗨,
什么卡不起作用? 它是连接到FPGA的子卡。 卡是通过较旧的时钟引脚连接到FPGA的。 这是关于rev 1.1和1.2的AR-http://www.origin.xilinx.com/support/answers/59751.html。 谢谢,AnirudhPS:请将此标记作为答案,以防它有助于解决您的问题。如果帖子引导您找到解决方案,请给予赞誉。 以上来自于谷歌翻译 以下为原文 Hi, What card does not work? Is it a daughter card connected to the FPGA. Is the card connected to the FPGA through the older clocking pins. Here is an AR on rev 1.1 and 1.2 - http://www.origin.xilinx.com/support/answers/59751.html. Thanks, Anirudh PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution. |
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