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嗨,
我想计算异步fifo的深度,但我很困惑如何计算它。 fifo参数如下: 写Clk Freq = 60 MHz。 读取Clk Freq = 100 MHz。 最大WriteBurst大小= 1024。 脉冲串写入之间的延迟= 4 clk。 ReadDelay = 2 clk。 任何人都可以帮助计算fifo深度的公式。 提前致谢...! 以上来自于谷歌翻译 以下为原文 Hi, I want to calculate depth of an async fifo, but I am confused how to calculate it. The fifo parameters are as follows: Write Clk Freq = 60 MHz. Read Clk Freq = 100 MHz. Maximum Write Burst Size = 1024. Delay between writes in burst = 4 clk. Read Delay = 2 clk. Can anyone help with the formula for calculating the fifo depth. Thanks in advance...! |
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嗨,
我想计算异步fifo的深度,但我很困惑如何计算它。 fifo参数如下: 写Clk Freq = 60 MHz。 读取Clk Freq = 100 MHz。 最大WriteBurst大小= 1024。 脉冲串写入之间的延迟= 4 clk。 ReadDelay = 2 clk。 任何人都可以帮助计算fifo深度的公式。 提前致谢...! 以上来自于谷歌翻译 以下为原文 Hi, I want to calculate depth of an async fifo, but I am confused how to calculate it. The fifo parameters are as follows: Write Clk Freq = 60 MHz. Read Clk Freq = 100 MHz. Maximum Write Burst Size = 1024. Delay between writes in burst = 4 clk. Read Delay = 2 clk. Can anyone help with the formula for calculating the fifo depth. Thanks in advance...! |
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检查以下链接,看看是否有帮助
http://forums.xilinx.com/t5/General-Technical-Discussion/FIFO-Depth-calculation/m-p/30903/highlight/true#M1313 --Krishna 以上来自于谷歌翻译 以下为原文 check the following link and see if this helps http://forums.xilinx.com/t5/General-Technical-Discussion/FIFO-Depth-calculation/m-p/30903/highlight/true#M1313 --Krishna |
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K,
那你写的每5个60 MHz时钟呢? 你读的每3个100 MHz时钟? 写入速率为12 MHz(60/5) 读取速率为33.3 MHz(100/3) 你的阅读速度比你写的要快...... Austin Lesea主要工程师Xilinx San Jose 以上来自于谷歌翻译 以下为原文 k, So every 5 60 MHz clocks you write? And every 3 100 MHz clocks you read? Write rate is 12 MHz (60/5) Read rate is 33.3 MHz (100/3) You are reading faster than you are writing... Austin Lesea Principal Engineer Xilinx San Jose |
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是的,我的阅读比写快,这就是为什么我很困惑如何计算深度。
那你写的每5个60 MHz时钟呢? 你读的每3个100 MHz时钟? 写入速率为12 MHz(60/5) 读取速率为33.3 MHz(100/3) 你如何得出上述结论。 我的写突发是1024,写突发之间的延迟是4 Wr_clk。 读延迟为2 Rd_clk。 以上来自于谷歌翻译 以下为原文 Yes my read is faster than write, thats why I am confused how to calculate the depth. So every 5 60 MHz clocks you write? And every 3 100 MHz clocks you read? Write rate is 12 MHz (60/5) Read rate is 33.3 MHz (100/3) How do u come up with the above conclusion. My write burst is 1024 and delay between write burst is 4 Wr_clk. Read delay is 2 Rd_clk. |
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嗨,
你的规格不是很精确,这会造成混乱。 现在写作似乎是这样的: 以60 MHz的速率,您有1024个字的数据突发,然后是4个时钟周期的暂停。 这意味着您在1028个时钟周期内传输1024个字(Tcycle = 1 / 60MHz)。 阅读部分仍不清楚。 是否像奥斯汀描述的那样: 1个读周期和2个暂停周期,导致1024个数据字的3 * 1024个周期 这意味着在3072个时钟周期内传输速率为1024字(Tcycle = 1 / 00MHz)。 或者你有一些(但未提及)爆裂读数在这里也是如此: 读取1024个字然后暂停2个时钟周期? 这意味着在1026个时钟周期内(Tcycle = 1 / 00MHz)传输1024个字。 你看,这有很大的不同。它会是什么? 或者它会完全不同吗? ___________ 读取数据比写入FIFO要快得多并不是什么大问题。 这就是空旗的用途。 如果FIFO为空,则停止读取。 (如果没有数据,则无需处理任何内容) 你在这种配置中的fifo可能非常小,因为你几乎可以立刻清空它。 但是,如果这是一种有用的方法,则取决于您的算法和设计架构。 通过检查写入侧的Full标志,也可以处理比读取更快的写入。 只有在大多数应用程序中,数据源通常会不加思索地泄露其数据,因此谴责以下硬件能够保持同步。 那你的申请是什么? 一些背景信息可以帮助理解问题。 有一个很好的综合 Eilert 以上来自于谷歌翻译 以下为原文 Hi, your specifications are not very precise, which causes confusion. Now for the writing it seems to be like this: At a rate of 60 MHz you have a data burst of 1024 words and then a pause of 4 clock cycles. Which means that you transfer 1024 words within 1028 clock cycles (Tcycle= 1/60MHz). The reading part is still unclear. Is it like Austin described: 1 read cycle and 2 pause cycles leading to 3*1024 cycles for 1024 data words Which means a transfer rate of 1024 words within 3072 clock cycles (Tcycle= 1/00MHz). Or do you have some (yet unmentioned) burst reading here as well like this: Reading 1024 words and then pause for 2 clock cycles ? Which means a transfer rate of 1024 words within 1026 clock cycles (Tcycle= 1/00MHz). You see there's a big difference. Which will it be? Or will it be something completely different? ___________ Reading data faster than they are writen to the FIFO is no big problem. That's what the Empty Flag is for. If the FIFO is empty, just stop reading. (If there's no data, nothing needs to be processed) Your fifo in such a configuration can be quite small, since you can empty it almost at once. However, it depends on your algorithms and design architecture if this is a useful approach. Writing faster than reading can also be handled, by checking the Full flag from the writing side. Only that in most applications data sources are often reclessly spilling out their data, condemning the following hardware to be able to keep the pace. So what is your application. Some background info can help to understand the problem. Have a nice synthesis Eilert |
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嗨艾勒特,
写作部分与您提到的完全相同。 在读取部分,我读了一个字,下一个时钟空闲,在下一个时钟我读了另一个字,即我在每个备用时钟上读。 以上来自于谷歌翻译 以下为原文 Hi Eilert, The writing part is exactly same as you have mentioned. In the reading part, I read one word, the next clock is idle and on the next clock I read another word i.e. I read on every alternate clock. |
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嗨,
所以你在2048个时钟周期内有一个1024字的数据速率(Tcyc = 1 / 100MHz)。 现在,您可以比较一个数据块的读取和写入时间,并检查您正在写入或读取更快。 根据该结果,您可以看到哪个标志(空/满)对您的数据流更为重要,并确定哪种FIFO大小最适合您。 其他设计属性也可能对此产生影响。 有一个很好的综合 Eilert 以上来自于谷歌翻译 以下为原文 Hi, so you have a datarate of 1024 words in 2048 clock cycles (Tcyc = 1/100MHz). Now you can compare the read and write times for one block of data and check wether you are writing or reading faster. According to that result you can see which Flag (empty/full) is more crucial for your data flow and decide which FIFO size works best for you. Other design properties might also have influence to this. Have a nice synthesis Eilert |
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有效深度将根据您生成的FIFO类型而有所不同。
对于通用时钟FIFO: 您选择的深度是您在通用时钟情况下将获得的实际深度。 对于独立时钟FIFO(Block Mem,Dist Mem类型): 在独立时钟的情况下,您接收的FIFO的物理深度实际上是您选择的深度。 但是,可用深度总是少一个。 在任何给定时间,不使用一个位置以防止write_pointer和read_pointer(内部指针)重叠。 如果这两个指针重叠,您将无法确定FIFO实际上是EMPTY还是FULL。 因此,可用深度总是少一个。 您可以将FIFO视为循环缓冲区。 对于FIFO16(独立时钟的通用): 在内置FIFO情况下,几个FIFO16基元级联在一起以形成所需的深度。 由于我们需要考虑每个这些原语的Full标志的延迟,我们使用每个这些原语的ALMOSTFULL标志来生成核心的FULL标志。 因此,使用每个基元,您将松开大约5个可用位置。 FIFO Gen GUI的最后一页是摘要页面,它将指示实际可用的深度。 谢谢和RegardsBalkrishan ----------------------------------------------- ---------------------------------------------请将帖子标记为 一个答案“接受为解决方案”,以防它有助于解决您的查询。如果一个帖子引导到解决方案,请给予赞誉。 以上来自于谷歌翻译 以下为原文 The effective depth will vary depending on the type of FIFO you generate. For common clock FIFOs: The depth you select is the actual depth you will receive in common clock case. For independent clock FIFOs (Block Mem, Dist Mem type): In the case of independent clocks, the physical depth of the FIFO you are receiving is actually the depth you have selected. However, the usable depth is always one less. At any given time, one location is not used in order to prevent the write_pointer and the read_pointer (internal pointers) from overlapping. If these two pointers were to overlap, you will not be able to determine if the FIFO is actually EMPTY or FULL. For this reason, the usable depth is always one less. You can think of FIFO as a circular buffer. For FIFO16 (common of independent clocks): In the built-in FIFO case, several FIFO16 primitives are cascaded together to form the desired depth. Since we need to account for the latency of the Full flag from each of these primitives, we are using ALMOSTFULL flags from each of these primitives for the generation of the FULL flag of the core. Therefore, with each of the primitives used, you will loose about 5 usable locations. The last page of the FIFO Gen GUI is the summary page, and it will indicate the actual usable depth. Thanks and Regards Balkrishan -------------------------------------------------------------------------------------------- Please mark the post as an answer "Accept as solution" in case it helped resolve your query. Give kudos in case a post in case it guided to the solution. |
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嗨!
谢谢大家的宝贵建议。 问候 以上来自于谷歌翻译 以下为原文 Hi! Thank you all for your valuable suggessions. Regards |
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