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嗨eveyone,
我是这个论坛的新人。 如果我弄错了,我道歉。 我正在尝试使用AXI Stream协议传输数据包。 这些数据包包括512 * 32位数据。 使用1 kHz时钟使能发送重新生成的数据包。 我的数据包结构:“ccccdddd”,“包计数器”,“00000000”,“00000000”,“00000000”,“00000000”,“00000000”,“00000000”,“deadbeef”,“deadbeef”,“deadbeef”, “deadbeef”,“deadbeef”,.........“deadbeef”,“deadbeef”,“deadbeef”。 正如我之前所说,我的数据包中包含512个双字。 介于9. - 512之间。数据相同(“deadbeef”)。 我可以在vivado仿真上正确看到这些数据包。 但是当我编程FPGA时,我无法在内存中正确读取数据包。 我正在使用“xaxidma_example_sg_intr”示例。 但我无法读取包装中的所有数据。 数据包从“01300000”地址开始。 但是在“01300520”,“013005A0”和“013006A0”地址上有意外的“00000000”数据。 并且在“013006F0”地址之后写入相关数据。 然后新的数据包在“01300800”地址后启动。 我附上了截图。有没有人可以帮助我? 谢谢。 以上来自于谷歌翻译 以下为原文 Hi eveyone, I am new on this forum. I apologize if I made a mistake. I am trying to transfer data packages by using AXI Stream protocol. These data packages include 512*32 bit data. Regenerated data packages are sent by using 1 kHz clock enable. My data package structure: "ccccdddd", "packet counter", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "deadbeef", "deadbeef", "deadbeef", "deadbeef", "deadbeef", ......... "deadbeef", "deadbeef", "deadbeef" . As I told before my data package include 512 double word. Between 9. - 512. data are the same ("deadbeef"). I can see these data packages properly on vivado simulation. But I can not read data packages properly on memory when I programmed FPGA. I am using "xaxidma_example_sg_intr" example. But I can not read all data in the package. Data package start at "01300000" address. But there are unexpected "00000000" data on "01300520", "013005A0" and "013006A0" address. And irrelevant data is written after "013006F0" address. Then new data package start after "01300800" address. I attached screenshot. Are there anyone who can help me? Thanks. |
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2个回答
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穆拉特,
这可能是缓存问题。 确保您执行的读取是针对更新的数据,而不是过时的缓存数据。 - 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。 以上来自于谷歌翻译 以下为原文 Murat, This could be a cache issue. Make sure that reads you do are against updated data, not to stale cached data. - Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. |
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你好,
我是穆拉特的同事,我们正在共同努力解决这个问题。 Murat正在处理硬件方面(FPGA代码),并通过修改“xaxidma_example_sg_intr”示例在Xilinx SDK中尝试他的硬件代码。 问题不是缓存问题,因为我们总是无效(如“while”语句中的屏幕截图)缓存数据,当我读取缓冲区描述符的状态寄存器时,我注意到实际传输的数据大小是“0x6f0”,这意味着一些 分组数据丢失。 让我重新解决我们的问题: 我通过使用axi流启动数据传输模块,然后通过在while块中使缓存无效来检查内存,以便查看写入的内容。 数据包由一个标题(0xCCDD)和一个递增包计数器组成,后面跟着6个零和数据值(0xDEADBEEF)。 添加开头的零只是为了跟踪内存。 当我检查内存时,注意到数据包(0xDEADBEEF)和数据包“0x6f0”之间存在一些意外的零,有一些不相关的数据。 请查看附件。 谢谢 modified_xaxidma_example_sg_intr.c 33 KB 以上来自于谷歌翻译 以下为原文 Hello, I m Murat's collegue and we are working on this issue together. Murat is dealing with hardware side (FPGA codes) and i m trying his hardware codes in Xilinx SDK by modifying "xaxidma_example_sg_intr" example. The problem is not a cache issue since we are always invalidating (as in screenshots in "while" statement) cache data and when i read the status register of Buffer Descriptors i notice that the actually transferred data size is "0x6f0" which means some of the packet data is lost. Let me resummarize our problem : I m starting a data transfer module by using axi stream, then checking the memory by invalidating the cache in a while block in order to see what is written. Data packet consists of a header (0xCCDD) an incrementing packet counter which is followed by 6 zeros and data values (0xDEADBEEF). Zeros at the beginning are added just for tracking the memory. When i inspected the memory i notice that there are some unexpected zeros between the data (0xDEADBEEF) and after "0x6f0" of data packet there are some irrelevant data. Please review the attached file. Thanks modified_xaxidma_example_sg_intr.c 33 KB |
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