顺序类型在块中未连接

查看您的代码，了解您正在使用的设备以及了解您正在使用的设计工具将会很有帮助。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
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以下为原文

It would be helpful to see your code, to know what device you are using, and to know what design tools you are using.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
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首先，这不是错误，而是警告。
它表示向量“xy_temp”的第0位和第39位
未连接（可能意味着“未使用”）。
通常这意味着这些
网将从设计中修剪。
如果这是xy_temp的预期用法
（即您对位0或39不感兴趣）然后您可以忽略警告。
-  Gabor
-  Gabor



以下为原文

First, this is not an error but a warning.  It says that bits 0 and 39 of vector "xy_temp"
are not connected (probably meaning "not used").  Generally this means that these
nets will be trimmed from the design.  If this is the expected usage of xy_temp
(i.e. you were not interested in bits 0 or 39) then you can ignore the warnings.
 
-- Gabor
-- Gabor

没有使用你的第39位和你在variablexy_temp中的第0位的meanes，我想你已经写了一个som代码，你只使用位的som作为输出信号
代码示例：
信号xy_temp：std_logic_vector（39 downto 0）;
an_output
这里编译器提醒您，位号39和0，未设置为任何输出端口，以防您不知道。



以下为原文

this meanes that your 39'th bit and your 0'th bit in the variable xy_temp is not used, i suppose that you have som code written where you only use som of the bits for the output signal
 
code example:
signal  xy_temp : std_logic_vector (39 downto 0);
an_output <= xy_temp(38 downto 1);
 
Here the compiler remind you that the bit number 39 and 0, is not set to any output port, just in case you didn't know.