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嗨,大家好,
我一直在使用Vivado设计套件一段时间了。 只是想知道 : 1.如果我可以通过链接Vivado使用Questasim 10.0b来验证设计? 2.我可以使用系统verilog编写testbech来模拟和验证verilog设计吗? 有人可以帮我这个。 [或指出任何有关此事的文件] 提前致谢。 谢谢& 问候, 专一 以上来自于谷歌翻译 以下为原文 Hi Guys, I have been using Vivado design suite for some time now. Just wanted to know : 1. If I could verify the design using Questasim 10.0b by linking the Vivado ? 2. Can I use system verilog for writing testbech to simulate and verify the verilog design ? Can somebody PLEASE help me with this. [or point me to any document regarding this] THANKS in advance. Thanks & Regards, Ananya |
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Helloananya.devraj@gmail.com,
是的,您可以使用系统verilog与Vivado Design Suite进行验证.Vivado模拟器支持可以合成的SystemVerilog RTL子集。 您需要检查UG下面的附录D,以了解支持的结构 http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_3/ug900-vivado-logic-simulation.pdf 问候,阿希什----------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - -请注意- 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。感谢Kudos .-------------------- -------------------------------------------------- ------------------------ 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Hello ananya.devraj@gmail.com, Yes you can use system verilog for verification with Vivado Design Suite. The Vivado simulator supports the subset of SystemVerilog RTL that can be synthesized. You need to check Appendix D from below UG to know the constructs which are supported http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_3/ug900-vivado-logic-simulation.pdf Regards, Ashish ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ----------------------------------------------------------------------------------------------View solution in original post |
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你好ananya.devraj@gmail.com,
Questasim 10.0b不支持Vivado 2014.3。 支持的版本是10.3b及以上。 有关支持的第三方工具,请查看Vivado 2014.3发行说明中的第16页: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_3/ug973-vivado-release-notes-install-license.pdf 是的,您可以使用系统verilog编写测试平台来验证verilog设计。谢谢,Syed -------------------------------------------------- --------------------------------------------请注意 - 请注明 如果提供的信息有用,请回答“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- --------------------- -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用,请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 Hello ananya.devraj@gmail.com, Questasim 10.0b is unsupported with Vivado 2014.3. The supported version is 10.3b and above. Check page number 16 in release notes of Vivado 2014.3 for supported third party tools: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_3/ug973-vivado-release-notes-install-license.pdf Yes, you can use system verilog for writing test bench to verify verilog design. Thanks, Syed ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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Sydez,
非常感谢您的快速回复。 还有一个疑问; 我可以使用System verilog和其他方法进行验证,即将Questasim 10.3b与Vivado连接吗? 谢谢& 问候, 专一 以上来自于谷歌翻译 以下为原文 Sydez, Thanks a lot for your quick reply. Just one more doubt; Can I use System verilog and other metodologies for verification purpose, i.e. by linking Questasim 10.3b with Vivado ? Thanks & Regards, Ananya |
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Helloananya.devraj@gmail.com,
是的,您可以使用系统verilog与Vivado Design Suite进行验证.Vivado模拟器支持可以合成的SystemVerilog RTL子集。 您需要检查UG下面的附录D,以了解支持的结构 http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_3/ug900-vivado-logic-simulation.pdf 问候,阿希什----------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - -请注意- 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。感谢Kudos .-------------------- -------------------------------------------------- ------------------------ 以上来自于谷歌翻译 以下为原文 Hello ananya.devraj@gmail.com, Yes you can use system verilog for verification with Vivado Design Suite. The Vivado simulator supports the subset of SystemVerilog RTL that can be synthesized. You need to check Appendix D from below UG to know the constructs which are supported http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_3/ug900-vivado-logic-simulation.pdf Regards, Ashish ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
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Helloananya.devraj@gmail.com,
“我可以使用System verilog和其他方法进行验证,即通过将Questasim 10.3b与Vivado连接起来吗?” 是的,您可以使用系统verilog与Vivado中的Questa sim 10.3b进行验证。 除非您已正确编写测试台,否则不应该有任何探测器。 --Syed -------------------------------------------------- --------------------------------------------请注意 - 请注明 如果提供的信息有用,请回答“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- --------------------- -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用,请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 Hello ananya.devraj@gmail.com, "Can I use System verilog and other metodologies for verification purpose, i.e. by linking Questasim 10.3b with Vivado ?" Yes, You can use system verilog for verification purpose with Questa sim 10.3b in Vivado. There shouldnt be any probelem unless you have properly written the test bench. --Syed ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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SYEDZ&
ASHISH, 谢谢你的支持。 非常有帮助。 谢谢& 问候, 专一 以上来自于谷歌翻译 以下为原文 SYEDZ & ASHISH, THANK YOU BOTH FOR YOUR SUPPORT. GREATLY HELPED. Thanks & Regards, Ananya |
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