怎么在文件中转储一个块RAM地址及其内容

嗨，
你在用什么模拟器？
测试平台的语言是什么？
我不确定ISIM是否也具备此功能，但对于Modelsim而言，它是
SignalSpy库。
在那里，您可以定义任何层次结构级别的信号路径。
但还有另一种可能的方法：
您可以使用一些assert命令来检测内存访问，并使用VHDL中的'image属性转储地址和数据的信号值。
或者，您可以使用某些文件io并将值写入某个文本文件。
所有这一切都可以在用于核心仿真模型的HDL包装器中完成，因此无论如何都可以从综合中幸免。
有一个很好的模拟 
Eilert



以下为原文

Hi,
what simulator are you using? And what language for the testbench?
I'm not sure if ISIM has this capability too,  but for Modelsim there's the
SignalSpy library.
There you can define a path to a signal in any hierarchy level.
 
But there's also an other possible approach:
You can use some assert command to detect memory access and dump out the signal values of address and data using the 'image attribute in VHDL.
Or, you can use some file io and write the values to some text file.
All of this can be done in the HDL wrapper for the simulation model of your core, so it is spared from synthesis anyway.
 
Have a nice simulation
  Eilert
 

1> Verilog2>此内存为1 x 16384（可以存储单个位，0或1）.Ports  -  clk，ena（内存启用），wea（erite启用），addra，dina，douta。在某些条件下都可以
ena和wea都是HIGH，可以将一个位写入内存。对于我来说，转储/写出地址（“addra”）值以及写入它的相应数据就足够了（“
迪娜“）。
我想在我的top-level_test-bench中做到这一点。还需要更多信息吗？
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以下为原文

1> Verilog

2> This memory is 1 x 16384 (It can store a single bit, 0 or 1).
Ports - clk, ena (memory enable), wea (erite enable), addra, dina, douta.
Under certain conditions both when ena and wea are HIGH, it is possible to write a single bit into the memory.
It would be sufficient for me to dump/write out to a file the address ("addra") value and the corresponding data being written to it ("dina"). I want to do it in my top-level_test-bench.
Any more info needed?--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
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我正在使用Synopsys的VCS。
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以下为原文

I am using VCS of Synopsys.--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
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放置代码将文件写入RAM模块本身会容易得多。
您可以在translate_off / translate_on pragma中添加模拟代码。
但是，大多数合成引擎无论如何都会忽略文件I / O，因此可能不需要它。
这当然只适用于行为模拟。
除此之外，如果使用层次结构，则可以从测试平台访问RAM。
这种方法的问题在于，如果要进行翻译后模拟，如果不在合成选项中专门保留层次结构，则层次结构可能会发生变化。
-  Gabor



以下为原文

It would be much easier to place the code to write the file inside the RAM module itself.  You can add the code for simulation within a translate_off / translate_on pragma.  However most synthesis engines will ignore the file I/O anyway so it may not be needed.  This of course is only going to work for behavioral simulation.  Other than that, it is possible to access the RAM from the testbench if you use the hierarchy.  The problem with this approach is that if you want to do post-translate simulation, the hierarchy can change if you don't specifically keep the hierarchy in the synthesis options.
-- Gabor

我必须从顶层使用层次结构来获取top_ level中的信号。
我正在使用$ writememb（“dump_file.txt”，memory_inst），当满足特定条件时，我得到了内存内容的转储。
但是因为在我的代码中，不止一次满足该特定条件，所以每次dump_file.txt都被覆盖并且我有最后的内存内容。
但是每次条件满足时，我都希望每次完整转储，附加到单个文件。
我怎样才能做到这一点？
我知道fwrite（），但无法弄清楚如何将$ writememb（）值附加到文件中。
这可能吗？
如果有，怎么样？
通用代码示例将很有帮助。
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以下为原文

I must do it from a top-level an dcurrently using hierarchy to get the signals in the top-level_tb.
 
I am using $writememb("dump_file.txt", memory_inst) and I get a dump of the memory contents when a particular condition is satisfied. But since in my code, that particular condition is satisfied more than once, so everytime dump_file.txt is being overwritten and I have the last memory contents.

 But I want the complete dump everytime, APPENDED to a single file, every time when the condition is satisfied. How can I do that?
I know about fwrite(), but cannot figure out how to append the $writememb() value to a file. Is this possible to do?
If yes how?
A generic code example will be helpful.
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FPGA enthusiast!
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Thanx很多Gabor。
最后我用文件写。
我从Xilinx CoreGen生成的内存是1x16384，即一个可以存储单个位的存储器，深度为16384.initial begin：memory_dump_out file_name = $ fopen（“file.txt”，“w +”）; endalways（@ posedge clk）
开始整数i;
if（某些条件满足）开始于（i = 0; i $ fwrite（file_name，“％b  n”，top_inst.top_next_inst ......... blk_mem_gen_v7_3_1x16384_inst.inst.native_mem_module.blk_mem_gen_v7_3_inst.memory [i
];结束$ fwrite（file_name，“----------------------------”）;努力
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以下为原文

Thanx a lot Gabor.
 
Finally I used file write. My mem generated from Xilinx CoreGen is 1x16384, ie, a memory which can store a single bit and is 16384 deep.

initial begin : memory_dump_out
    file_name = $fopen("file.txt", "w+");
end

always (@ posedge clk) begin
  integer i;
  if (some condition is satisfied) begin
     for (i=0; i<16384; i=i+1) begin
        $fwrite(file_name, "%b n", top_inst.top_next_inst.........blk_mem_gen_v7_3_1x16384_inst.inst.native_mem_module.blk_mem_gen_v7_3_inst.memory;
     end
    $fwrite(file_name, "----------------------------");
  end
end
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FPGA enthusiast!
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