如何在块ram中加载RGB的所有值？

您基本上是在询问如何设计您所描述的内容，这是正确的吗？
您有什么FPGA设计经验？
您的第一步是定义设计要求，包括您要存储的图像的大小。
你有这样的设计定义吗？
下一步是将设计定义转换为程序框图。
你有新设计的方框图吗？
然后，您需要更详细地描述设计中的每个块 - 足够的细节以清楚地描述您的Verilog或VHDL实现代码。
最后，您将详细的设计描述逐个时间转换为HDL代码。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
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我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

You are basically asking how to design what you have described, is this correct?
 
What experience with FPGA design do you have?
 
Your first step is to define the requirements of your design, including the size of the image you wish to store.  Do you have such a design definition?
 
Your next step is to transform your design definition to a block diagram.  Do you have a block diagram for your new design?
 
Then you need to describe each block in your design with more detail -- enough detail to clearly describe your Verilog or VHDL implementation code.
 
Finally, you translate the detailed design description, block by clock, into HDL code.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
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2. Search the forums (and search the web) for similar topics.
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Virtex-5的内部RAM不是DDR。您可以在FPGA内部存储的最大图像大小取决于您需要多少位/像素，但是相当小：196 * 18Kb每个存储48 * 18Kb，
如果你需要24位/像素，由于内存组织，这将提供24k像素/图像。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

The internal RAM of Virtex-5 is not DDR.

The maximum size of image you can store internal to the FPGA will depend on how many bits/pixel you need, but will be rather small:
196 * 18Kb gives 48 * 18Kb per store,
and if you need 24 bits/pixel, because of the memory organisation, that will give 24k pixels/image.
------------------------------------------
"If it don't work in simulation, it won't work on the board."

我的图像是24位/像素，即彩色图像。
我想将每个图像元素存储在内部RAM中，即R G和B颜色值。
因此，我需要四个块ram（一个额外用于存储Temp阵列），其大小为100 x 100像素
什么方式我这样做?????
谢谢



以下为原文

My image is 24bits/pixel i.e colour image .
 
I want to store each element of image i.e R G and B colour values in internal RAM.
 
So in all I need four block ram (one extra for storing Temp array) of size say 100 by 100  pixels
 
whats d way i do it?????
 
Thanks

你在哪里读这个图像？
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

Where are you reading this image from?

------------------------------------------
"If it don't work in simulation, it won't work on the board."

非常感谢回复....我正在尝试从我的计算机硬盘驱动器中读取图像。我在c中有图像：驱动此图像我必须阅读到virtex 5 fpga的块公羊



以下为原文

Thanks alot for reply....


I am trying to read image from my computer harddrive.


Say i have image in c: drive this image i have to read into block rams of virtex 5 fpga

“假设我在C：驱动器中有图像，这是我要写入Virtex-5 FPGA的BlockRAM的图像。”您需要在PC上运行一些软件，通​​过通信通道将文件发送到电路板上。
FPGA on。需要FPGA中的补充固件才能从通信通道接收图像数据，并将其写入BlockRAM的所需区域。
很多你要学习的东西！你有什么板？
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

"Say I have image in C: drive and it is this image I want to write into BlockRAMs of the Virtex-5 FPGA."

You will need some software running on the PC that sends the file via a communication channel to the board with the FPGA on.
There will need to be complementary firmware in the FPGA to receive the image data from the communication channel, and write it into the desired area of BlockRAM. A lot of learing for you to do!

What board do you have?

------------------------------------------
"If it don't work in simulation, it won't work on the board."

我有ML505，它有串口和USB两个接口。我想使用串行接口。可以从@PC到@ ML505串行缓冲区以十六进制代码的形式输入图像。然后我将在hdl中写一个代码，这将是
当任何数据到来时，它会连续监视SBUFF，然后将其串行放入RAM.Then我将开始计算结果的算法。这个结果应该通过在hdl中输入总和UART发送模块来发送，然后将结果发送回@ pc.I am
有24位的图像。它是彩色图像，这就是为什么24位。我想玩所有24位图像。请指导我这个。



以下为原文

I am having ML505 and it is having serial and USB both interface.
I m thinking of using serial interface .
Means inputting image in the form of hex codes from @PC to @ML505 serial buffer.
Then i will write a code in hdl which will continuosly monitor the SBUFF when any data comes then serially put it to block RAM.
Then i will start my algo for calculating result .
This result should be send by wrting sum UART transmit module in hdl to send that result back to @pc.
I am having image of 24 bit .
It is colour image thats why 24 bit.
I want to play with all 24 bits of image.
Please guide me on this.

“请指导我。”设计和测试是小阶段。
首先采用LED闪烁设计，以获得对工具的信心。
然后分阶段进行设计。例如，接下来进行PC  - > FPGA通信.PC是否需要从FPGA返回一些返回值以指示FPGA已接收数据？FPGA如何知道它何时获得
它需要的所有数据？
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

"Please guide me on this."

Design and test is small stages.
Do an LED-blinking design FIRST OF ALL to get confidence with the tools. Then proceed with your design in stages.
For instance, get the PC -> FPGA communications up next.
Does the PC need some return value back from the FPGA to indicate that the FPGA has received data?
How does the FPGA know when it has got all the data it needs?

------------------------------------------
"If it don't work in simulation, it won't work on the board."

是的，当FPGA获得总图像**哔哔**文本文件然后在收到完整文件后它应该计算结果。我将知道计算发生了因为我将设置图像大小限制因此我知道将有多少HEX字节
文本文件。



以下为原文

Yes when FPGA get total image **bleep** text file then after receiving complete file it should compute the result.
I will know that computations happened coz i will be setting the image size constraints so i know how many HEX bytes will be der in  text file.

现在做进一步的研究我知道我应该总是把图像的数量或大小放在图像文本文件的开头。这个计数将是十六进制代码。所以一旦我得到大小的十六进制字节，我将为相同的值设置计数器
。并使用计数器值我会做所有的计算。



以下为原文

Now doing further study I got to know that I should always put count or size of image at the start of image text file.This count will be in hex code.So once I get hex byte of size I will set counter for the same value.and using counter value I will do all the computation.