如何在VHDL/Verilog中实现流量生成器

您好Tablekursi，
你能详细说明一下流量发生器是什么意思吗？
你有什么规格可以详细说明吗？
感谢致敬
Shreyas
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以下为原文

Hi Tablekursi,
 
can you please elaborate more on what do you mean by traffic generator. are there any specifications that you can tell in detail?
 
Thanks and Regards
Shreyas
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你好，
您可以选择更好的语言，Xilinx支持Verilog和VHDL。
转到更新版本。
从我的项目要求中可以看出，你应该选择有限状态机（FSM）。
为您的设计编写适当的代码和约束。
借助功能仿真确保您的设计正常工作。
如果您的设计通过功能仿真，则进行综合然后进行综合后仿真。
在生成的网表上运行实现，检查时序违规。
生成比特流并将其下载到目标FPGA。
FYI ..
这是一般方法。
谢谢，
Anusheel
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以下为原文

Hello,
 
You can choose preferable language, both Verilog and VHDL are supported by Xilinx.
 
Go for the updated version.
 
As I can see from your project requirement you should go for Finite State Machines (FSM).
 
Write appropriate code and constrains for your design.
 
Make sure your design is working fine with the help of functional simulation.
 
If your design passes functional simulation go for synthesis then post-synthesis simulation.
 
Run implemetation on your generated netlist, check for timing violations.
 
Generate bitstream and download it to targeted FPGA.
 
FYI..
This is general approach. 
 
 
Thanks,
Anusheel
 
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嗨，
看起来对此有实质性的讨论，如果你还没有得到它的信息，请详细说明你的问题
http://forums.xilinx.com/t5/New-Users-Forum/traffic-generator/m-p/247428#M1155
问候，
Vanitha
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以下为原文

Hi,
 
It looks to be there is substantial discussion on this, if you have not got enougs info from it please eloborate your question
http://forums.xilinx.com/t5/New-Users-Forum/traffic-generator/m-p/247428#M1155
 
Regards,
Vanitha
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