XST错误旁路

你可以删除“reg clkIn;”
线。
“输入clkIn”语句已经声明clkIn是一个连线并重新声明它，因为reg不是必需的。一行让我困惑的是“clkIn这看起来完全是假的。我认为你的意思是clkOut; //和laterclkOut？
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以下为原文

You can just remove the "reg clkIn;" line. The "input clkIn" statement already declares clkIn to be a wire and redeclaration of it as reg is not necessary.
One lines which baffles me is "clkIn <= (count == 4'b0000); "
This looks completely bogus. I think you meant
reg clkOut; // and later
clkOut <= (count == 4'b0000);
?- Please mark the Answer as "Accept as solution" if information provided is helpful.
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你可以删除“reg clkIn;”
线。
“输入clkIn”语句已经声明clkIn是一个连线并重新声明它，因为reg不是必需的。一行让我困惑的是“clkIn这看起来完全是假的。我认为你的意思是clkOut; //和laterclkOut？
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。



以下为原文

You can just remove the "reg clkIn;" line. The "input clkIn" statement already declares clkIn to be a wire and redeclaration of it as reg is not necessary.
One lines which baffles me is "clkIn <= (count == 4'b0000); "
This looks completely bogus. I think you meant
reg clkOut; // and later
clkOut <= (count == 4'b0000);
?- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

谢谢你帮助解决了这个错误。
但是其他事情也出现了。
因为这是一个时钟分频器，它需要与原始输入一起工作。
现在，当我运行模拟时，时钟以200MHz的速率滴答，但是如果我添加clkOut，则频率没有变化（即，它可能将它分开但没有连接到clkIn输入）。
如何将输入clkIn连接到clkOut寄存器，以便它在模拟中分开。
下面是测试台的代码：
模块ethernettest;
//输入reg clkIn;
//输出有线Ethernet_TDp;
电线Ethernet_TDm;
电线clkOut;
//实例化被测单元（UUT）packet_sender uut（.clkIn（clkIn）,. Ethernet_TDp（Ethernet_TDp），。CONTnet_TDm（Ethernet_TDm）,. clkOut（clkOut））;
初始开始clkIn = 0;
//初始化输入结束始终开始＃500 clkIn = 1;
＃500 clkIn = 0;
//等待100 ns进行全局重置以完成＃100;
//在这里添加刺激结束endmodule



以下为原文

Thank you this helped with the error. But somthing else arised. becasue this is a clock divider it needs to work with the orginal input. Right now when I run a simulation the clock ticks at 200MHz but if I add clkOut, there is no change to the frequency (i.e while it may dividing it is not connected to the clkIn input).
 
 
How can I connect the input, clkIn, to the clkOut register so that it divides in a simulation. 
 
below is the code for the test bench: 
 
module ethernettest;
// Inputs
reg clkIn;
// Outputs
wire Ethernet_TDp;
wire Ethernet_TDm;
wire clkOut;
// Instantiate the Unit Under Test (UUT)
packet_sender uut (
.clkIn(clkIn),
.Ethernet_TDp(Ethernet_TDp),
.Ethernet_TDm(Ethernet_TDm),
.clkOut(clkOut)
);
initial begin
clkIn=0;
// Initialize Inputs
end

always begin
#500 clkIn= 1;
#500 clkIn = 0;
// Wait 100 ns for global reset to finish
#100;

// Add stimulus here
end


endmodule
 

我认为你的问题是你的测试平台没有创建时钟。
从always块中删除clkIn赋值并将以下内容添加到初始块：clkIn = 0; forever＃500 clkIn =！clkIn;这应该为您提供一个不断切换的时钟而不是单个脉冲。
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。



以下为原文

I think your problem is that your testbench does not create a clock. remove the clkIn assignments from always block and add the following to the initial block:
clkIn = 0;
forever #500 clkIn = !clkIn;

This should give you a constantly toggling clock as opposed to a single pulse.- Please mark the Answer as "Accept as solution" if information provided is helpful.
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