怎么读取USB批量传输到FX2LP

我有cy7c68014a-56pvxc有一个自制的小木板。它插在我的SabThan-3 FPGA板上。我配置EP2在TRM描述（fig.9.28）是这样的：cpucs = bmclkspd1；/ / 48mhz syncdelay()；ifconfig = 0xa3；/ /驱动ifclk内部30mhz时钟，使用同步FIFO。syncdelay()；revctl = 0x03；syncdelay()；ep2cfg = 0xa2；syncdelay()；fiforeset = 0x80；syncdelay()；fiforeset = 0x82；syncdelay()；fiforeset = 0x00；syncdelay()；outpktend = 0x82；syncdelay()；outpktend = 0x82；syncdelay()；ep2fifocfg = 0x10；syncdelay()；FPGA驱动器fifoadr0和fifoadr1低，和断言SLRD和黑刺李总（即它总是准备接受数据时，数据是可用的）。然后我尝试了一些情况：1）FPGA ifclk上升沿计数，带FLAG标签说“不空”。如果主机发送1024个字节，FPGA显示1024个数。到现在为止，一直都还不错。二）FPGA的计算输入数据位校验，使用相同的时间为（一）。如果主机发送1024个字节，FPGA显示校验符合它接收1024字节，包括256份字节字节1字节513字节3 512 256份256份256份0）FPGA数转换（即当前字节不同于上），使用相同的钛明代为（1）。如果主机发送1024个字节，所有零除buf [ 0 ] = 1，但是[ 1 ]，但[ 512 ] = 2，但是[ 513 ] = 3，FPGA显示器0x3ff。这样看来，每个512字节块，FX2LP芯片发送正确的字节数的FPGA，但它只是发送0字节1字节的交替，扔掉一切。就好像，Slave FIFO用来从端点缓冲区读9位偏移被掩盖而递增的正确端口不知这只是0,1,0,1,0,1,0,1。结果是，不论512字节块的数量发送，校验和（二）从上面出来的笔在每个块的第一个字节对256倍。所以我的问题是，我只是在做傻事（缺少登记initialisations？）或者我在某种程度上破坏了我的FX2LP？我试着完全相同的实验用6，与相同的结果。其他功能的FX2LP我测试（如自定义EP0命令，EEPROM &；内存负载）似乎是工作的罚款。衷心感谢您的帮助！克里斯编辑：我能正确读取USB批量传输到FX2LP，所以我怀疑这是我从FIFO配置错误的东西。



     以下为原文
          I have a small home-made board with a CY7C68014A-56PVXC on it. It plugs into my Digilent Spartan-3 FPGA board. I configure EP2 as described in the TRM (fig.9.28) like this:   
   
CPUCS = bmCLKSPD1; // 48MHz   
SYNCDELAY();   
IFCONFIG = 0xA3; // drive IFCLK with internal 30MHz clock, use synchronous FIFOs.   
SYNCDELAY();   
REVCTL = 0x03;   
SYNCDELAY();   
EP2CFG = 0xA2;   
SYNCDELAY();   
FIFORESET = 0x80;   
SYNCDELAY();   
FIFORESET = 0x82;   
SYNCDELAY();   
FIFORESET = 0x00;   
SYNCDELAY();   
OUTPKTEND = 0x82;   
SYNCDELAY();   
OUTPKTEND = 0x82;   
SYNCDELAY();   
EP2FIFOCFG = 0x10;   
SYNCDELAY();   
   
The FPGA drives FIFOADR0 and FIFOADR1 low, and asserts SLRD and SLOE always (i.e it's always ready to accept data when data is available). I then tried a number of scenarios:   
   
1) FPGA counts IFCLK rising edges for which FLAGC says "not empty". If the host sends 1024 bytes, the FPGA shows a count of 1024. So far so good.   
   
2) FPGA calculates a 16-bit checksum of incoming data, using the same timing as in (1). If the host sends 1024 bytes, the FPGA shows a checksum consistent with it receiving 1024 bytes, comprising:   
   
256 copies of byte 0   
256 copies of byte 1   
256 copies of byte 512   
256 copies of byte 513   
   
3) FPGA counts transitions (i.e where the current byte differs from the last), using the same timing as in (1). If the host sends 1024 bytes, all zero except buf[0]=1, buf[1] = buf[512] = 2, buf[513] = 3, the FPGA displays 0x3FF.   
   
So it looks like for each 512 byte chunk, the FX2LP chip is sending the correct number of bytes to the FPGA, but it is just sending byte 0 alternating with byte 1, and throwing away everything else. It's as if the 9-bit offset which the slave FIFO uses to read from the endpoint buffer is being masked with 0x0001 somehow so rather than incrementing properly it just goes 0,1,0,1,0,1,0,1. The result is that irrespective of the number of 512-byte chunks sent, the checksum from (2) above comes out as 256 times the sum of the first pair of bytes in each chunk.   
   
So my question is, am I merely doing something silly (missing register initialisations?) or have I damaged my FX2LP in some way?   
   
I tried the exact same experiments with EP6, with exactly the same results. The other functions of the FX2LP which I have tested (e.g custom EP0 commands, EEPROM & RAM loads) appear to be working fine.   
   
Any help gratefully received!   
   
- Chris   
   
Edit: PS I can correctly read back USB bulk transfers to the FX2LP, so I suspect it's something wrong with my slave FIFO config.