AN65974从设备FIFO卡在FLAGA高电平且FLAGB为低电平时

我确实修改了SLaveFio2ByStuilin.v（附件）中给出的示例，以便能够发送打包成32位字的字节流（使用Xilinx FIFO内核）。很自然地，SLWR现在不一直保持低电平，但当FIFO输出无效时，SLWR变高。
不幸的是，经过这一修改，一旦旗杆变低，它将永远保持低位。
为了复制它，我修改了测试平台FPGA-MasktiP.V（附加）来模拟FX3行为，这是我所理解的。
从我看到的，如果FLAB变低，但是我没有写足够的单词来填充整个DMA缓冲区，DMA就不会被刷新。
我是否正确理解我只有两种选择：
确保一旦FLAB低到刷新DMA，我总是把确切的字数写为缓冲区大小的驱动器PKKAND低。否则，FLAB将永远保持低位。
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     以下为原文
  I did modify the example given in slaveFIFO2b_streamIN.v (attached) to be able to send the stream of bytes packed into 32 bit words (using  Xilinx FIFO core). Quite naturally the SLWR now doesn't stay low all the time, but goes high when FIFO output is not valid.
    Unfortunately after this modification once FLAGB goes low it stays low forever.
    To reproduce it I did modify the test bench fpga_master_tb.v (attached) to simulate the FX3 behavior to the best of my understanding.
    From what I see if FLAGB goes low, but I don't write enough words to fill entire DMA buffer, the DMA will not get flushed.
    Do I understand correctly that I have only two options:
   

     
• Make sure that I always write exact number of words as a buffer size
• Drive PKTEND low once the FLAGB is low to flush the DMA.
  

    Otherwise FLAGB will stay low forever.

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