端口映射后信号会变得嘈杂

嗨，大家好，
我遇到了一些奇怪的信号特征，我想我可能会找到一些帮助。
我有一个顶级vhdl代码，它有多达5个串联的模块，因为数据从一个模块流向另一个模块。
数据时钟速率为54MHz。
我正在使用chipcope pro，在167MHz的采样频率下进行调试。
现在我注意到，当我将端口映射到第五个模块时，来自第四个模块的一些信号变得非常嘈杂。
第五个模块的任务是读取这些信号并将它们存储到fifo中。
我在下面贴了一些chicpscope pro图片，以便你可以欣赏它们的不同之处。
请注意端口映射后信号8_6和7_7如何变得非常嘈杂。
所有其他信号（8_7,8_11,3_11等）由第五个模块在同一指令读取，但只有8_6和7_7变为有噪声。
我该如何排序这个问题。
我尝试使用中间信号，但无济于事。
谢谢你的时间。
最好的祝福



以下为原文

Hi guys,

I have met with some strange signal characteristics and I thought I might find some help.

I have a top-level vhdl code which has up to 5 modules connected in series in the sense that data is being pipelined from one module to the other. Data clock rate is at 54MHz. I'm using chipscope pro, at a sampling freuqnecy of 167MHz for debugging.

Now I notice that some signals, coming from the fourth module become very noisy as soon as I port map them to the fifth module. The task of the fifth module is to read these signals and store them into a fifo. I have posted some chicpscope pro pictures below so that you may appreciate the difference.

Please notice how signals 8_6 and 7_7 become very noisy after portmapping. All the other signals (8_7,8_11,3_11 etc) are being read by the fifth module at the same instruction yet only 8_6 and 7_7 become noisy.

How can I sort this issue. I tried using an intermediate signal but at no avail.

Thanks for your time guys.

Best regards