PSoC 5LP ADC SAR序列，速率为1MHz怎么实现

你可能需要把这个例子作为数据表规范，模拟全局，
引用的是Delsig输入，当然是从一个设计到另一个设计。
路线可以不同。所以在博士论文中没有简短的答案。
假设1V VREF稳定到1 LSB，这里是计算器（您可以使用）
欧姆计工具获取路线R和捏造C）
HTTP://DeaveToS.Actudio.COM/DT/Stutel/SealLe.HTML
在柏树创建一个技术或问题案例
CyPress网站
“支持”
“技术支持”
“创造一个案例”
你必须先在赛普拉斯网站上注册。
问候，Dana。



     以下为原文
  You might have to post a CASE on this as datasheet specs, analog globals,
    are referenced to DelSig input, and of course from one design to another
    route can be different. So no short answers in the docs.
     
    Assuming a 1V Vref settling to 1 LSB, calculator here (you could use
    ohmmeter tool to get route R and fudge the C)
     
        
              http://designtools.analog.com/dt/settle/settle.html
     
        
             
    To create a technical or issue case at Cypress -
     
    www.cypress.com
    “Support”
    “Technical Support”
    “Create a Case”
     
    You have to be registered on Cypress web site first.
     
    Regards, Dana.

实现12位精度，8通道多路复用器与1 MHz ADC veryunlikely测序。这一切都取决于时间的沉淀，它甚至在50欧姆的负载将几微秒。我没有尝试与PSoC，但它能与高端DAQ板比较，在1MHz信道之间的串扰，我看到相当大。这里的现实结合的速度becomestypically 200khz 100OHM负载和~ 1%跨-渠道之间的谈话。
消除串扰通常推荐复用/交替采样通道接地，使每一个利用ADC测量是在地面完成，短的剩余电量。另一种方法来提高相声istohave所有measuredvoltages是同一尺度，否则1%串扰从1V通道将彻底破坏10mv测量下通道。
奥迪赛1



     以下为原文
  Achieving 12 bit accuracy with 8 channel MUX with 1 MHz sequencing ADC is very unlikely. It all depends on the settling time, which even on 50 oHm load will be few usec. I didn't try it with PSoC, but can compare it with high-end NI-DAQ boards, where I see considerable cross-talk between channels at 1MHz. Here realistic combined speed becomes typically 200kHz with 100oHm loads and ~1% cross-talk between channels. 
         To eliminate cross-talk it is typically recommended to MUX/interleave sampling channels with GND, so that each 2-nd ADC measurement is done on the GND, to short the remaining charge. Another way to improve cross-talk is to have all measured voltages to be of the same scale, otherwise 1% crosstalk from 1V channel will completely spoil 10mV measurement of next channel.
    odissey1    

这里有一个例子（你可以骗取自己13位值）
~（36）ns
从AP笔记上的ADI工具沉降时间页
相对于相声，有在使用delsig作为负载数据表规格
＞100分贝。也许，当你的文件，你的情况，问是否可以代表
在SAR路由中的串扰。
问候，Dana。



     以下为原文
  Here is an example (you can diddle the values yourself) to 13 bits is
    ~ 36 nS -
     
     
     
    From the ap note on the ADI tool settling time page -
     
     
     
    With respect to crosstalk, there is a spec in datasheet using DelSig as the load
    of > 100 db. You might, when you file your case, ask if that would be representative
    of the crosstalk in a SAR route.
     
    Regards, Dana.

我在PSoC5LP数据表（表11-31）中看到，开关和路由电阻将是大约1000欧姆，但是缺少的信息是SAR ADC的输入电容。
在每个转换周期的18个时钟（56Ns周期）中，信号必须是稳定的4个时钟（获取窗口），留下约750nS的沉降。如果SAR ADC输入电容为150 pF，则τ~1k×150 pf= 150纳秒，i具有约5个时间常数来解决。如果输入电容大于此，则可以将运算放大器连接为缓冲器（数据表表11-19，输入电容＝18pF），但是如果从运算放大器输出到SAR ADC的路由电阻仍然为1KOHM，则没有任何帮助。
我有一个案子公开，所以我会看看他们说什么。



     以下为原文
  I see in the PSoC5LP data sheet (Table 11-31) that the switch and routing resistance is going to be around 1000 ohms, but the missing information is the input capacitance of the SAR ADC.
    Of the 18 clocks (56ns period) per conversion cycle, the signal must be stable for 4 clocks (acquisition window), leaving about 750ns for settling. If the SAR ADC input capacitance is 150 pf, then tau ~ 1K x 150pf = 150ns and I have about 5 time constants to settle. If the input capacitance is bigger than that, I could connect an op amp as a buffer (data sheet Table 11-19, input capacitance = 18pf) but that's no help if the routing resistance from op amp output to SAR ADC is still 1Kohm.
    I have a case open so I will see what they say.

如果你使用欧姆表工具，你可以得到路线R的概念。
如果SAR输入C，你可能会提出一个案子，150的PF看起来非常高。
占用大量的模具面积。你也可以指出TIA R公差是-25%到+35%，
似乎Muxs应该跟踪？这是我的猜测，因为mux Rdson非常依赖。
在VGSON上，也许这就是离开的原因。也许他们有更好的表征数据
在特定的VDD中运行部分。
在柏树创建一个技术案例
CyPress网站
“支持”
“技术支持”
“创造一个案例”
你必须先在赛普拉斯网站上注册。
问候，Dana。



     以下为原文
  If you use the ohmmeter tool you can get an idea of route R -
     
     
     
    Insofar as SAR input C you might file a CASE on this, 150 pF seems incredibly high, would
    take up a lot of die area. You might also point out the TIA R tolerances are - 25% to + 35%,
    seems like muxes should track ? This is a guess on my part as mux Rdson is very dependent
    on Vgson, maybe thats why the departure. Maybe they have better characterization data for
    running part at a specific Vdd.
     
        
             
    To create a technical case at Cypress -
     
    www.cypress.com
    “Support”
    “Technical Support”
    “Create a Case”
     
    You have to be registered on Cypress web site first.
     
    Regards, Dana.

可能的CulpIT将不是RC，而是MUX切换时间（约1U）和ADC运算放大器转换速率（约1V/US）。将这些值添加到ADC计算器中可以得到大约500 kHz的采样率。
不管怎样，看到实际的表演会很有趣。完成后请分享您的项目。
奥迪赛1



     以下为原文
   The likely culpit will be not RC, but MUX switching time (about 1us) and ADC OPAMP slew rate(approx. 1V/us). Adding those values into ADC calculator gives about 500kHz sampling rate.
     
    Anyway, it will be interesting to see actual performance. Please share your project when done.
    odissey1

有趣的是PSoC 4架构TRM状态-
CTBM输出通过SARBUS0／1（在1 MSPS下不足够快到山姆PLE）
AuxBuxAA/Y-B（不足以在1 MSPS上取样）
当您询问文件时，PSoC 4是否与5LP族相同的几何/过程。
运放在高功率、200 pF负载下的SR为3 V/US，太差了。
15 PF或更相关的东西。
你可以设置一个MUX测试，测量它是否只是柏树。
过于保守
问候，Dana。



     以下为原文
  Interestingly enough the PSOC 4 Architecture TRM states -
     
    CTBm output via sarbus0/1 (not fast enough to sam
ple at 1 Msps)


     
      
     AMUXBUS_A/_B (not fast enough to sample at
1 Msps)

     
     
     
      
    When you file CASE ask if the PSOC 4 is the same geometry/process as the 5LP family.
     
     
    The SR of the OpAmp at high power, 200 pF load, is ~ 3 V/uS, too bad its not speced
    with 15 pF or something more relevent.
     
    You could always set up a mux test and measure it just to see if Cypress is
    overly conservative.
     
     
    Regards, Dana.

只是这个讨论带来一点清晰…
SAR ADC被设计为允许硬件延迟时间为零，这意味着您可以使用硬件驱动的MUX在前面，并且在总共1个MSPS或每通道125 kSPS的情况下运行SAR，而不存在显著的串扰问题。当对输入信号进行采样时，SAR发出一个通常称为“下一个”的信号。这通常被用作触发输入多路复用器到下一个信道的触发器，并且您有一个慷慨的~ 0.75的交换发生。这当然假设MUX直接连接到SAR。它把复用和SAR之间的一个放大器不是一个好主意（除非是超级快）；如果你需要什么样的条件，给每一个信自己的放大器。
SAR的有效输入电容是~八PF和它将负责为12bit足够的时间只要源电阻2.3k或不准确。现在，很大一部分是由内部的路由消耗，所以最好的假设是全速运行仅仅是小于几百欧姆的低阻抗源。如果你有高阻抗源，缓冲他们用放大器，给你一个至少6兆赫你想获得闭环带宽。PSoC放大器将实现在单位增益，但你可能需要如果你想显著更大的增益使用外部零件。
我还没有找到内在的研究工作尚未对8通道配置，但我们研究了双通道配置在PSoC 4a相当深入每通道500 KSPS，并清楚地表明，没有明显的通道间的串扰与默认的采样设置和低阻抗Si来自发电机的GNALS。我们甚至连的情况下，一个通道是故意虐待，和不寻常的行为被看到。
希望有点帮助！



     以下为原文
   Just to bring a bit of clarity to this discussion...
    The SAR ADC is designed to permit hardware muxing with zero latency - meaning that you can use a hardware-driven mux on the front, and run the SAR at an aggregate 1 Msps, or 125 ksps per channel, without significant crosstalk issues.  The SAR issues a signal usually referred to as 'next' when it is done sampling the input signal.  This is typically used as the trigger to click the input mux onto the next channel and you have a generous ~0.75 us for the switching to happen.  This assumes of course that the mux is connected direct to the SAR.  It's not a good idea to put an amplifier between mux and SAR (unless it is super super fast); if you need any kind of conditioning, give each channel its own amplifier.
    The effective input capacitance of the SAR is ~8 pF and it will charge to 12bit accuracy in enough time as long as the source resistance is 2.3k or less.  Now, quite a lot of that is consumed by the internal routing, so the best assumption is that the full-speed operation is only for low impedance sources of less than a few hundred ohms.  If you have high impedance sources, buffer them - with an amplifier that gives you a closed-loop bandwith of at least 6 MHz at the gain you want.  PSoC amplifiers will achieve this at unity gain, but you may need to use external parts if you want significantly greater gain.
    I haven't found internal research work yet on the 8-channel configuration, but we studied the 2-channel configuration at 500 ksps per channel on PSoC 4A quite intensively, and showed clearly that there was no significant interchannel crosstalk with the default sampling settings and low impedance signals from generators.  We even checked the case where one channel was deliberately overdriven, and no unusual behaviour was seen.
    Hope that helps a little!

KVCP感谢澄清的答案。你所说的一切都同样适用于PSoC5LP和PSoC4吗？
我的印象是PSoC4在SAR ADC附近有专用MUX切换，而PSoC5LP使用GPIO PIN开关。这可能表明PSoC5LP的MUX总线路由电容被添加到原始ADC。
我的应用程序将进入CY8C5868 LTI LP038。
扔出



     以下为原文
  @kvcp Thanks for the clarifying answer. Does everything you say apply equally to PSoC5LP and PSoC4?
    I was under the impression that PSoC4 has dedicated mux switching near the SAR ADC while PSoC5LP uses the GPIO-pin switches. That might suggest that PSoC5LP's mux bus routing capacitance is added to the raw ADC.
    My application is going into a CY8C5868LTI-LP038.
     
    Chuck

PSoC 5LP SARS在1 MSPS下运行不会有问题。假设你的外部信号具有较低的输出阻抗和不使用内部PGA或放大器。默认情况下，SAR ADC的时钟将在18 MHz，因此将需要18钟全转换。第一四个时钟（默认）是采集时间，或时间允许的SAR ADC的输入电容器充电。这个输入帽大约是8或10pF。你可以增加采集时间对PSoC 5lp如果你需要更多一点的时间来解决。它不是为psoc4 SAR采集时间那样灵活，但它是可用的。
沉淀的另一半从销向SAR输入。这部分电路几乎4倍的时间去解决。如果我没记错的话，一个时钟采样后是完整的，这个信号变高，让测序硬件内部地址复用器切换到下一个频道。这意味着输入信号可以解决所有的方式向SAR输入开关几乎全转换周期或几乎整个美国。当ADC开始重新采样，输入上限将在最后一个通道相同的电压，所以它必须与新的价值/放电电荷输入帽。
我知道你在想什么，一旦你开始再次采集阶段，内部路由电容不可能完全overwelm输入电容。没错，但至少它有一个开端。如果路由加源电阻太高，可以增加与adc_sar_1_sar_csr2_reg登记采集时间。价值观是怪异的1到7种，128, 256, 384，等等，但总比没有好。PSoC 4 SAR能够改变这个值，我认为2到1000，在1个时钟的步骤。
希望这有帮助，
作记号



     以下为原文
  The PSoC 5LP SARs should have no problem running at 1 MSPS.  Assume that you external signal has a relatively low output impedance and you are not using the internal PGAs or opamps.  By default the SAR ADC clock will be at 18 MHz so it will take 18 clock for a full conversion.  The first four clocks (by default) is the acquisition time, or the time allowed to charge the input capacitor of the SAR ADC.  This input cap is about 8 or 10pF.  You can increase this acquisition time on the PSoC 5LP if you need a little more time to settle.  It isn't as flexible as the PSoC4 SAR acquisition time, but it is usable. 
    The other half of the settling is from the pin to the input to the SAR.  This part of the circuit has almost 4 times more time to settle.  There If I remember correctly, one clock after the sampling is complete, this signal goes high letting the sequencing hardware switch the internal AMUX to the next channel.  this means that the input signal can settle all the way to the input switch of the SAR for almost a full conversion cycle or almost an entire us.  When the ADC starts to sample again, the input cap will be at the same voltage of the last channel, so it will have to charge/discharge the input cap with the new value. 
    I know what you are thinking, once you start the acquisition phase again, the internal routing capacitance may not totally overwelm the input capacitor.  Correct, but at least it had a head start.  If the route plus your source resistance is too high, you can increase the acquisition time with the ADC_SAR_1_SAR_CSR2_REG register.  The values are kind of wierd 1 thru 7, then, 128, 256, 384, etc, but better than nothing.  The PSoC 4 SAR you can change this value from I think 2 to over 1000, in 1 clock steps.
    Hope this helps,
     
    Mark

这额外的信息是非常有用的，我感到鼓舞，这是可行的。我们将有一个CY8CKIT-050B开发工具包，我将做一些验证测试。如果有人想发布或发送一个PSoC Creator项目来测试，我很乐意运行它。
正如我现在理解的，这里有两个时间常数。首先，GPIO-AMUXBUS切换改变状态。所选信号通过由（1）外部源电阻组成的电阻对分布式路由电容进行充电-在我的情况下～75欧姆；（2）激活开关；（3）AMUXBUS电阻。这个总的名义上是500欧姆（Dana的探测，我还没有使用过这个工具），可能是温度、电源电压等的两倍，所以说1000欧姆是最坏的情况。我还没有听说AMUXBUS电容可能是什么，但只要它小于80 pF左右，750毫秒将有足够的时间来解决1 LSB。假设它是20pF。
当SAR ADC采集窗（250 ns）打开时，第二时间常数开始发挥作用。AMUXBUS 20PF上的电荷将通过ADC中的开关与SAR输入电容（8PF）相等。这个时间常数大约是8pF倍，开关路径电阻（几百欧姆）和电荷将很快地平衡（可能是15纳秒到1LSB）。然而，这仅得到其最终值的电压（20/28）或70%。剩余的30%的电荷必须在剩余时间内通过全路由电阻转移到全路由电容（加上ADC输入电容）。用我的数字，时间常数是1000欧姆×28 pF= 28 ns，并且因为我已经70%个家，我只需要7个时间常数来解决1LSB，即200毫秒。唷，我想我做到了！如果没有，我可以调整一个控制寄存器，并允许更多的时间来获取窗口；但是，如果我这样做，我将不得不减去1ms /秒，我没有太多的摆动空间。
干杯，
扔出



     以下为原文
  This additional info is very useful and I feel encouraged that this can work. We will have a CY8CKIT-050B dev kit soon and I will be doing some verification tests. If anyone wants to post or send me a PSoC Creator project for testing I'd be happy to run it.
     
    As I understand it now there are TWO time constants here. First, the GPIO-AMUXBUS switches change state. The selected signal charges the distributed routing capacitance through a resistance consisting of (1) external source resistance -- in my case ~75 ohms; (2) the activated switch; (3) the AMUXBUS resistance. This total will nominally be ~500 ohms (ref Dana's probing; I haven't used that tool yet) and might be up to double that depending on temperature, supply voltage, etc. So say 1000 ohms worst case. I haven't heard what the AMUXBUS capacitance is likely to be, but as long as it's less than 80 pf or so 750 nsec will be plenty of time to settle within 1 LSB. Let's say it is 20pf.
     
    The second time constant comes into play when the SAR ADC acquisition window, 250 ns long, opens. The charge on the AMUXBUS's 20pf will equalize with the SAR input capacitance (8pf) through a switch in the ADC. This time constant will be roughly 8pf times the switch path resistance (a few hundred ohms) and charge will equalize pretty quickly (maybe 15 ns to 1LSB). However this only gets the voltage (20/28) or 70% of the way to its final value. The remaining 30% of the charge has to transferred through the full routing resistance to the full routing capacitance (plus ADC input capacitance) in the remaining time. With my made-up numbers that time constant is 1000 ohms x 28pf = 28ns, and because I'm already 70% home I only need 7 time constants to settle to 1LSB, i.e. 200 nsec. Whew, I think I just made it! If not, I can tweak a control register and allow more time for the acquisition window; however if I do that I will have to derate from 1Ms/sec and I don't have much wiggle room there.
     
    Cheers,
      Chuck

我认为如果MEH和KVCP把他们的知识汇集到一起，那就太好了。
一张美钞，或者一页纸的白纸。很有价值。
包括SAR前端的实际架构讨论。
但那只是我的想法。
问候，Dana。



     以下为原文
  I think it would be great if meh and kvcp pooled their knowledge into
    an ap note, or a one page white paper at minimum. Quite valuable.
    Include actual architecture of SAR front end discussion.
     
    But then thats just my thought.
     
    Regards, Dana.

利用CY8CKIT-050B对DC相邻信道串扰测试的一些初步测试结果：
1782MHz ADC时钟，0～3.3V ADC范围，4个采集时钟（默认），100欧姆源电阻，4 LSB串扰。
1782MHz ADC时钟，0～3.3V ADC范围，7个采集时钟，100欧姆源电阻，3 LSB串扰。
1782MHz ADC时钟，0～3.3V ADC范围，128个采集时钟，100欧姆源电阻，0 LSB串扰。
台架试验条件不完善，所以我不认为这些结果是决定性的。
扔出



     以下为原文
  FYI, some preliminary test results from a DC adjacent-channel crosstalk test using CY8CKIT-050B:
     
    17.82MHz ADC clock, 0-3.3V ADC range, 4 acquisition clocks (default), 100 ohm source resistance, 4 LSB crosstalk.
    17.82MHz ADC clock, 0-3.3V ADC range, 7 acquisition clocks, 100 ohm source resistance, 3 LSB crosstalk.
    17.82MHz ADC clock, 0-3.3V ADC range, 128 acquisition clocks, 100 ohm source resistance, 0 LSB crosstalk.
    Bench test conditions were not perfect so I do not consider these results definitive.
     
    Chuck

具有100欧姆源R i的预期最大2 LSB，本征
+/- 1 LSB转换不确定度。可能来自处理器的附加噪声
与输入路径串扰无关。
如果你说这些数据源在K范围，结果对我来说似乎很高。
然后我会想好的，好的。
也许用MUX来接未使用的输入可能会有帮助？
如果平均读数是一个符号，则不相关的噪声被去除，
注意处理噪声通常与内部过程高度相关，
钟。
也许赛格可以对此发表评论。
问候，Dana。



     以下为原文
  With 100 ohms source R I would have expected at most 2 LSBs, intrinsic
    +/-1 LSB conversion uncertainty. Maybe additional noise from processor
    not related to crosstalk of the input routes contributing.
     
    Results seem high to me, if you said these were at K range of source R
    then I would have thought OK, good.
     
    Maybe grounding unused inputs with mux might help.....?
     
    If you average readings this is a sign uncorrelated noise is being removed,
    note processsor noise generally highly correlated to internal processes,
    clocks.
     
    Maybe seg can comment on this.
     
    Regards, Dana.