如何在ISE和EDK项目中共享ML605差分clk

你是什​​么意思“ise and edk”？
这是硬件连接，不应与软件相关。
差分clk可以通过OBUFDS实现。



以下为原文

what do you mean "among ise and edk"? this is hardware connection and should not be related with software. differential clk can be achieved through OBUFDS.

假设有两个VHDL模块，COMPONENT EDK_modulePORT（CLK_P：在std_logic中; CLK_N：在std_logic中; ------ ------）; END COMPONENT; COMPONENT ISE_modulePORT（CLK_P：在std_logic中; CLK_N：在std_logic中）
; ------ ------）; END COMPONENT;如果ML605板有跟随网clk_in_p LOC = J9 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE; NET clk_in_n LOC = H9 | IOSTANDARD = LVDS_25 | DIFF_TERM =
TRUE;差异clk，1）如何将上述时钟映射到两个组件（EDK_module和ISE_module）？（它不能直接映射，因为它们将共享相同的clk缓冲区）2）关于回复注释，如何制作
通过OBUFDS差异clk？



以下为原文

Assume, there are two VHDL modules,

COMPONENT EDK_module
PORT (
      CLK_P                          : in  std_logic;
      CLK_N                          : in  std_logic;  
      ------
      ------
);
END COMPONENT;

COMPONENT ISE_module
PORT (
      CLK_P                          : in  std_logic;
      CLK_N                          : in  std_logic;  
      ------
      ------
);
END COMPONENT;

If the ML605 board has a following

NET  clk_in_p        LOC = J9   |IOSTANDARD = LVDS_25  |DIFF_TERM = TRUE;
NET  clk_in_n        LOC = H9   |IOSTANDARD = LVDS_25  |DIFF_TERM = TRUE;

differential clk,

1) How can I map the above clock to both components (EDK_module and ISE_module)?
(It can't be mapped directly as they will share the same clk buffer)

2) Regarding the reply comment, how to make a differential clk through OBUFDS?

简短的回答：你不能，但你也不应该。
差分信号仅存在于器件的引脚上，并在IOB中转换为单端的（I / O）BUFDS组件。
每个差分对只有一个IBUFDS。
选项1：在设计的HDL部分中实例化ibufds和bufg，并将时钟路由到EDK和HDL设计的其余部分。
您可能需要修改edk设计，以便它不会尝试实例化输入缓冲区和全局时钟。
选项2：让edk实例化ibufds和bufg，然后将时钟从bufg上的EDK设计中路由出来，以供HDL设计的其余部分使用。



以下为原文

Short answer: You cannot but you shouldn't need to either.
Differential signals only exist at the pins of the device and are converted in the IOB to single ended with (I/O)BUFDS components. There is only a single IBUFDS for each differential pair.
 
Option 1:  Instantiate the ibufds and bufg in the HDL portion of the design and route the clock to EDK and the rest of the HDL design.  You will probably need to modify the edk design so it doesnt try to instantiate the input buffer and global clock.
 
Option 2: let edk instantiate the ibufds and bufg and then route the clock out of the EDK design on the bufg for the rest of the HDL design to use.