在FPGA中实现HDMI，DVI和DisplayPort输入的可行性

我不认为任何软处理器核心能够以高分辨率直接驱动这些接口，因此您应该为显示控制器使用某种HDL接口。
有一个Xilinx TFT控制器IP可能会做你想要的（尽管可能没有），如果你想了解DVI-D的低级细节，那就有XAPP495。
您不需要处理器，但是否有一个处理器将取决于您的要求。
如果你想实现一个漂亮的GUI，处理器可能就是你要走的路。
要只输出FFT的可视化表示，你可能会在没有一个聪明编码的情况下离开。



以下为原文

I don't think any soft processor core will be able to drive these interfaces directly at high resolutions, so you should use some sort of HDL interface for the display controller. There's a Xilinx TFT controller IP that might do what you want (though possibly not) and there's XAPP495 if you want to find out about the low level details of DVI-D.
 
You don't need a processor, but whether or not one will be useful will depend on your requirements. If you want to implement a nice GUI, a processor is probably the way to go. To just output a visual representation of an FFT, you could probably get away without one with some clever coding.
 
 

非常感谢，joelby。
我看了一下Xilinx TFT控制器IP，它看起来不像我想要的。
这是因为它只支持640x480分辨率，而我们需要1080P。
它看起来XAPP495提供了有趣的信息。
我会仔细检查。现在，一般的想法是，我们需要在FPGA内部使用IP来控制显示端口。
如果我将处理器放入FPGA内，那么控制器IP可以将其连接到处理器，然后处理器可以进行进一步处理。
但是，这是不必要的，没有处理器，系统仍然可以工作，对吧？非常感谢。



以下为原文

Thanks very much, joelby. I had a look at the Xilinx TFT controller IP, it does not look like what I want. This is because it only supports  640x480 resolution, instead we need 1080P. It looks XAPP495 provides interesting information. I will check it carefully.

Now, the general idea is, we need IP inside the FPGA to control the display ports. If I put a processor inside the FPGA, then the controller IP can connect it to processor, then processor can do the further processing. However, this is unnecessary, without processor, the system can still work, right?

Thanks very much.

我刚刚意识到另一个问题是：对于实现HDMI，DVI和Displayport，我们是否需要千兆位收发器？非常感谢。



以下为原文

I just realized another question is: for implement HDMI, DVI, and Displayport, do we need gigabit transceiver or not?

Thanks very much.

现在，一般的想法是，我们需要FPGA内部的IP来控制显示端口。
如果我将处理器放入FPGA内，那么控制器IP可以将其连接到处理器，然后处理器可以进行进一步处理。
但是，这是不必要的，没有处理器，系统仍然可以工作，对吗？
我真的不明白这个问题。
“控制显示端口”是什么意思？
某些IP被设计为连接到处理器（例如，如果它具有AXI总线），但如果您实现自己的AXI总线，则不必使用处理器。
如果你看看XAPP495，它没有实现像AXI那样的任何东西，你会发现处理器不需要做简单的显示切换并显示固定的模式。
我从未处理过DisplayPort，但对于HDMI和DVI，您可以使用普通的LVDS I / O（通常也是HDMI缓冲芯片）。
如果您需要获得更高的分辨率，SERDES块将有所帮助。
也许做一些谷歌搜索是否有其他人用FPGA实现DisplayPort你可能能够找出他们是否需要使用外部收发器芯片或PHY等，或者查看你选择的分辨率所需的比特率和
看看这是否在您正在考虑的FPGA部件上的SERDES功能范围内。



以下为原文

Now, the general idea is, we need IP inside the FPGA to control the display ports. If I put a processor inside the FPGA, then the controller IP can connect it to processor, then processor can do the further processing. However, this is unnecessary, without processor, the system can still work, right?

I don't really understand the question. What do you mean by 'control the display ports'? Some IP is designed to be connected to a processor (e.g. if it has an AXI bus) but you don't have to use a processor if you implement your own AXI bus.
 
If you look at XAPP495, which doesn't implement anything fancy like AXI, you'll see that a processor isn't required to do simple display switching and to display a fixed pattern.
 
I've never dealt with DisplayPort, but for HDMI and DVI you can get away with normal LVDS I/Os (and usually an HDMI buffer chip, too). SERDES blocks will help if you need to achieve higher resolutions. Perhaps do some Googling to see if anyone else has implemented DisplayPort with an FPGA and you might be able to find out if they needed to use a external transceiver chip or PHY or something, or look at the bit rate required by your resolution of choice and see if this is within the capabilities of SERDES on the FPGA part you're considering.
 

谢谢，joelby。
目前，我更喜欢没有porcessor的实施。
参考设计如xapp460和xapp495，他们不使用处理器。
需要TMDS I / O而不是LVDSIéO。
是否需要SERDEs块取决于我想要的分辨率。



以下为原文

Thanks, joelby. Currently, I prefer that implemention without porcessor. The reference design like xapp460, and xapp495, they dont use processor. TMDS I/O is needed instead of LVDS IéO.

Whether SERDEs blocks are needed, depends on the resolution I want.