XEM6010时钟频率如何改变

我在ISE上为这款蛋白石凯利板写了一个4位计数器verilog程序。
但我不知道如何改变时钟频率，以便我可以看到Led在计数开始时打开或关闭。
将计数器的大小从4位增加到14位，并使用最高4位作为输出。
低10位将用作1024分频时钟分频器或预分频器。
对于不同的分频因子，使用更多位或更少的位。
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以下为原文

I have written a 4 bit counter verilog program on ISE for this opal kelly board. But i don't know how to change the clock frequency so that i can see the Led's turning on or off as the counting starts.
 
Increase the size of the counter from 4 bits to 14 bits, and use the most significant 4 bits as your output.  The low-order 10 bits will serve as a divide-by-1024 clock frequency divider or pre-scaler.  Use more bits or fewer bits for different divide factors.
 
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README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

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