有没有办法明确分配特定的I/O芯片垫？

是的，这是可能的，但正如其他人所指出的那样，非粘合垫的用例非常少。
如果在FPGA_EDITOR中选择未绑定的焊盘，它将显示它的站点名称和焊盘名称（请参见下面的快照）。
LOC可以使用IO到站点或填充名称。
例如
NET di LOC = UNB_X0Y259;
olufola写道：
您是否希望将IO信号分配给裸片上的未粘合焊盘？
我只想知道它是否可能？
它没有提到
约束指南！
我想你是想说Xilinx省略了
故意因为它没有解决任何已知问题。
干杯，吉姆
在原帖中查看解决方案



以下为原文

Yes, it's possible but as it's pointed out by others there are very few use cases of unbonded pads. If you select an unbonded pad in FPGA_EDITOR, it will show it's site name and pad name (see the snapshot below). LOC an IO to either site or pad name should work. e.g
 
NET di LOC = UNB_X0Y259;
 

 
 

olufola wrote:
Do you wish to assign IO signals to unbonded pads on the die?


I only want to know if it is possible? It was not mentioned in the
Constraints Guide! I guess you are trying to say that Xilinx omitted
it deliberately because it does not solve any known problem.

Cheers,
JimView solution in original post

显式包装引脚分配在.UCF文件中进行，该文件是一个易于编辑的文本文件。
例如：
NET“ShutterRls1_n”IOSTANDARD = LVCMOS33 |
DRIVE = 6 |
SLEW =“慢”|
pullup |
LOC = C13;
您是否希望将IO信号分配给裸片上的未粘合焊盘？
如果是这样，也许您可​​能会找到时间来描述通过此操作解决的问题 - 也许可能会向您建议另一种方法。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Explicit package pin assignments are made in the .UCF file, a text file which is easily edited.  For example:
 
NET "ShutterRls1_n" IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = "SLOW" | pullup | LOC = C13;
 
Do you wish to assign IO signals to unbonded pads on the die?  If so, perhaps you might find the time to describe the problem which is solved by this maneuver -- and perhaps an alternate approach may be suggested to you.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

嗨鲍勃，
我知道封装引脚分配是在.UCF文件中进行的。
我想确保以下想法是正确的：
1.芯片上的焊盘是连接到封装引脚的芯片焊盘
2.未粘合的焊盘未连接到任何封装引脚
之所以出现这个问题是因为我刚刚仔细研究了Xilinx约束指南，并且没有限制将端口分配给未绑定的芯片焊盘（如果我对未绑定焊盘的定义是正确的）。
谢谢。



以下为原文

Hi Bob,
 
I am aware that package pin assignments are made in the .UCF fIle. I want to be sure that the following ideas are correct:
1. bonded pads on the die are die pads that are connected to package pins
2. unbonded pads are not connected to any package pins
The question arose because I just finished a careful study of the Xilinx Constraints Guide and there is no constraint to assign ports to unbonded die pads (if my definition of unbonded pads is correct).
 
Thank you.

1.芯片上的焊盘是连接到封装引脚的芯片焊盘
2.未粘合的焊盘未连接到任何封装引脚
是的，根据定义，在两点上。
你有兴趣回答我在上一篇文章中提出的问题吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

1. bonded pads on the die are die pads that are connected to package pins
2. unbonded pads are not connected to any package pins
 
Yes, by definition, on both points.  Are you interested in answering the question I posed in previous post?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

您是否希望将IO信号分配给裸片上的未粘合焊盘？
我只想知道它是否可能？
它没有提到
约束指南！
我想你是想说Xilinx省略了
故意因为它没有解决任何已知问题。



以下为原文

Do you wish to assign IO signals to unbonded pads on the die?


I only want to know if it is possible? It was not mentioned in the
Constraints Guide! I guess you are trying to say that Xilinx omitted
it deliberately because it does not solve any known problem.

是的，这是可能的，但正如其他人所指出的那样，非粘合垫的用例非常少。
如果在FPGA_EDITOR中选择未绑定的焊盘，它将显示它的站点名称和焊盘名称（请参见下面的快照）。
LOC可以使用IO到站点或填充名称。
例如
NET di LOC = UNB_X0Y259;
olufola写道：
您是否希望将IO信号分配给裸片上的未粘合焊盘？
我只想知道它是否可能？
它没有提到
约束指南！
我想你是想说Xilinx省略了
故意因为它没有解决任何已知问题。
干杯，吉姆



以下为原文

Yes, it's possible but as it's pointed out by others there are very few use cases of unbonded pads. If you select an unbonded pad in FPGA_EDITOR, it will show it's site name and pad name (see the snapshot below). LOC an IO to either site or pad name should work. e.g
 
NET di LOC = UNB_X0Y259;
 

 
 

olufola wrote:
Do you wish to assign IO signals to unbonded pads on the die?


I only want to know if it is possible? It was not mentioned in the
Constraints Guide! I guess you are trying to say that Xilinx omitted
it deliberately because it does not solve any known problem.

Cheers,
Jim

我完全满意地回答了这个问题。
鲍勃和吉姆给你一个很大的“谢谢”。



以下为原文

The question was answered to my full satisfaction. A big "Thank You" to Bob and Jim.