vhdl代码帮助

大家好，
我必须在clk的每个上升沿发送1个D阵列。
下面是我的代码请帮我完成代码。
entity data_sense isport（clk：在std_logic中; --addr：在整数范围0到3; data_out：out std_logic_vector（15 downto 0））; end data_sense; architecture data_sense的行为istype vector_array是std_logic_vector的数组（0到3）（
15 downto 0）;信号存储器：vector_array;信号地址：整数范围0到3;  - 类型vector_array1是std_logic_vector的数组（0到3）（15 downto 0）;  - 信号temp：vector_array1;信号temp：std_logic_vector（
15 downto 0）; beginmemory（0）（15 downto 0）内存（1）（15 downto 0）内存（2）（15 downto 0）内存（3）（15 downto 0）进程（clk） - 变量temp：
std_logic_vector（15 downto 0）; beginfor i in 0 to 3 loopif（clk'event and clk ='1'）thentemp end if if; end loop; end process; data_out end Behavioral;我必须一个接一个地发送4个数组
clk的所有上升边缘:)
请帮忙。
谢谢



以下为原文

Hi all,

I have to send  1 D array  at each  rising edge of the clk. below is my code please help me to complete the code.

entity data_sense is
port(       clk : in std_logic;
             --addr : in integer range 0 to 3;
         data_out : out std_logic_vector(15 downto 0));
end data_sense;

architecture Behavioral of data_sense is
type vector_array is array(0 to 3) of std_logic_vector(15 downto 0);
signal memory : vector_array;
signal addr  : integer range 0 to 3;
--type vector_array1 is array(0 to 3) of std_logic_vector(15 downto 0);
--signal temp : vector_array1;
signal temp : std_logic_vector(15 downto 0);
begin
memory(0)(15 downto 0) <= "1111000011110000";
memory(1)(15 downto 0) <= "1111000011110000";
memory(2)(15 downto 0) <= "0111000011110000";
memory(3)(15 downto 0) <= "1111000011110000";
process(clk)
--variable temp : std_logic_vector(15 downto 0);
begin
for i in 0 to 3 loop
if(clk'event and clk = '1') then
temp <= memory(i)(15 downto 0);
end if;
end loop;


end process;
data_out <= temp;

end Behavioral;

I have to send 4 array one by one repeatedly at all the rising edge of the clk :)

Please help.

Thanks