完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
嗨,
我不确定这是否是发布它的正确位置。 我一直在Simulink(matlab 2011a)和窗口7上使用Xilinx System Generator(不确定这是否正确名称)。我只获得了“Viterbi Decoder”评估许可证。 我重新启动了电脑。 我试图使用“Viterbi Decoder 7.0”和“Viterbi Decoder 8.0”块并获得以下消息; 许可证失败 - 块的必需Hardware_Evaluation或Bought许可证 “HDL网表生成”期间发生错误。 “模拟初始化”期间发生错误。 Xilinx模块库中发生内部错误。 请尽可能详细地将此错误报告给Xilinx(http://support.xilinx.com)。 您也可以在http://support.xilinx.com上的Answers数据库和其他在线资源中找到即时帮助。 “HDL网表生成”期间发生错误。 “模拟初始化”期间发生错误。 有一个类似的案例 http://forums.xilinx.com/t5/DSP- ... em/m-p/307233#M6553 但是,他可以使用“Viterbi Decoder 7.0”。 我不能。 不知道如何解决这个问题。 谢谢 以上来自于谷歌翻译 以下为原文 Hi, I am not sure if this is the right place to post it. I have been using Xilinx System Generator (not sure if this is right name to call it) on Simulink (Matlab 2011a) and window 7. I just got “Viterbi Decoder” evaluation license. I have rebooted my computer. I have tried to use both “Viterbi Decoder 7.0” and “Viterbi Decoder 8.0” blocks and got following message; License failure - Required Hardware_Evaluation or Bought license for the block Error occurred during "HDL Netlist Generation". Error occurred during "Simulation Initialization". An internal error occurred in the Xilinx Blockset Library. Please report this error to Xilinx (http://support.xilinx.com), in as much detail as possible. You may also find immediate help in the Answers Database and other online resources at http://support.xilinx.com. Error occurred during "HDL Netlist Generation". Error occurred during "Simulation Initialization". There is a similar case in http://forums.xilinx.com/t5/DSP- ... em/m-p/307233#M6553 But, his can use “Viterbi Decoder 7.0”. Mine can not. Do not know how to fix this problem. Thanks |
|
相关推荐
7个回答
|
|
你好
我们已经看到系统生成器没有正确检测维特比解码器许可证的问题。 您正在使用的ISE版本是什么。 ISE14.3应与viterbi Decoder 7.0配合使用 还要检查核心生成器或xinfo文件中的许可证状态,检查此核心的许可证是否正确选择。 问候,萨蒂什----------------------------------------------- --- --------------------------------------------请注意 - 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用的帖子。感谢.-- ---------------------------- --------------------- ---------------------- 以上来自于谷歌翻译 以下为原文 Hi We have seen issues with System generator not detecting the viterbi Decoder licenses properly. What is the ISE version you are using. ISE14.3 should work with viterbi Decoder 7.0 Also check if the license for this core is picking correctly by checking the license status in the core generator or xinfo file. Regards, Satish ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful. --------------------------------------------------------------------------------------------- |
|
|
|
你好,谢谢你的回复。
我刚刚安装了ISE。 但是,我的窗口告诉我它是Xilinx ISE Design Suite 13.4。 我的“管理Xilinx许可证”标签显示“viterbi_v4_0”。任何建议?谢谢 以上来自于谷歌翻译 以下为原文 Hi, Thanks for your reply. I just installed ISE recently. But, my window tells me it is Xilinx ISE Design Suite 13.4. My “Manage Xilinx Licenses” tag shows “viterbi_v4_0”. Any suggestion? Thanks |
|
|
|
你好
你可以发布你的xinfo文件和维特比解码器许可证文件。 问候,萨蒂什----------------------------------------------- --- --------------------------------------------请注意 - 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用的帖子。感谢.-- ---------------------------- --------------------- ---------------------- 以上来自于谷歌翻译 以下为原文 Hi Can you post your xinfo file and the viterbi decoder license file. Regards, Satish ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful. --------------------------------------------------------------------------------------------- |
|
|
|
嗨,
你有解决过的错误吗? 如果有任何解决方法,请告知。 我也在处理类似的错误。 提前致谢 !!! 问候, Hardik Purohit yenigal写道: 你好 你可以发布你的xinfo文件和维特比解码器许可证文件。 以上来自于谷歌翻译 以下为原文 Hi, Did you gor solution of subjected error ? Please advise if any workaround is available. I am also dealing with similar error. Thanks in advance !!! Regards, Hardik Purohit yenigal wrote: |
|
|
|
喜...
你解决了这个问题,因为我遇到了与维特比解码器7.0和8.0版本相同的问题。 亲切的我在哪里z问题.. 以上来自于谷歌翻译 以下为原文 hi... Did you solve that problem because i m getting same problem with viterbi decoder 7.0 and 8.0 version. Kindly intimate me where z the problem.. |
|
|
|
Hellosushma @ 22,
您是否真的拥有此IP核的硬件_评估或购买许可? 如果没有,您可以从www.xilinx.com/getlicenses获取此Viterbi解码器核心的硬件评估许可证。 *任何IP内核的硬件评估许可证都允许您在设计中参数化,生成和实例化这些内核。 您还可以执行功能和时序仿真,并生成可用于在硬件中下载和配置设计的比特流。 IP核将在编程设备中完全正常运行一段时间。 在此之后,IP将“超时”(停止运行),您将需要再次下载和配置FPGA。 如果您有任何疑问,请告诉我。 亲切的问候, 阿纳托利 亲切的问候,Anatoli Curran,Xilinx技术支持----------------------------------------- --------------------------------不要忘记回复,工作,并接受解决方案.---- -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 Hello sushma@22, Do you actually have a Hardware_Evaluation or Bought license for this IP Core? If not, you can obtain a Hardware Evaluation license for this Viterbi Decoder Core from www.xilinx.com/getlicenses. * A Hardware Evaluation license for any of the IP cores will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware. The IP cores will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again. If you have any questions, please let me know. Kind Regards, Anatoli Kind Regards, Anatoli Curran, Xilinx Technical Support ------------------------------------------------------------------------- Don’t forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
|
|
|
你好
得到黑盒子的问题..最初我在ISE webpack中写了一个带有四个子.vhd文件的vhdl代码。那个代码加载到黑盒子里,显示NAN输出甚至黑盒属性被修改成ISE模拟器..有任何 加载所有这些文件的其他程序..请回复此邮件ID koyeladasushma@gmail.com ..我正在研究系统生成器,但只是我在学习阶段,所以请尽快回复我。 以上来自于谷歌翻译 以下为原文 Hi Getting problem with black box block.. Initially I wrote a vhdl code with four sub .vhd files in ISE webpack.. That code is loaded into black box, showing NAN output even black box property is modified into ISE simulator.. There is any other procedure to load all those files.. Kindly give reply this mail id koyeladasushma@gmail.com.. I am working on system generator, but just i am in a learning stage so kindly reply me as soon as possible. |
|
|
|
只有小组成员才能发言,加入小组>>
2380 浏览 7 评论
2797 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2262 浏览 9 评论
3335 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2428 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
756浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
545浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
366浏览 1评论
1963浏览 0评论
682浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-11-23 01:45 , Processed in 1.323707 second(s), Total 90, Slave 73 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号