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我深入到UDB,需要创建一个以PoS5LP为目标的动态PI组件。我用手工在Verilog中创建设计的勇气,但是我使用DATAPATH配置工具来设置ALU指令。 在创建组件时,我以PSoC5LP为目标,而不是通用设计。 因此,CFG15—14中的PI-DYN位变灰了,我不能调用它。 阅读以下文章: 从并行输入(非A0或A1)输入的数据路径ALU 我看到PSOC5有一个问题,这意味着动态PI不起作用,但后来的评论表明这是固定在PSoC5LP。因此,我认为数据路径工具在我想使用PSoC5而不是PSoC5LP的印象中是错误的。 我在我的代码中有一些定义,假设我定义了哪些设备: “定义CyDeLoScIPHyMeMARE5A 3” “定义CyDeLoCHIPSIMPARE5B 2” “定义CyDeVelCHIPHyMySype使用2” 更多的搜索表明CyDaveCHIPSMeNeMy5a=PSoC5和CyDeVelChIPMeMySub 5b是PSoC5LP,因此它意味着选择了正确的设备,但我找不到如何定义这些设备的描述,并且随机调整对这种情况没有帮助。 任何指导如何获得Dyn PI为PSoC5LP启用或指针到正确的文件将非常感谢。 当做 齐格 以上来自于百度翻译 以下为原文 Hi, I'm deep into the UDB and need to create a component with a dynamic PI aimed at PSoC5LP. I am creating the guts of the design in verilog by hand, but am using the Datapath Config Tool to setup the ALU instructions. When creating the component I target the PSoC5LP rather than crating a generic design. As a result the PI DYN bit in CFG15-14 is greyed out and I cannot invoke it. Reading the following post: Datapath ALU input from Parallel Input (not A0 or A1) I see that there was an issue with PSoC5 that means dynamic PI does not work, but later comments suggest this is fixed in PSoC5LP. So I am presuming that the datapath tool is incorrectly under the impression that I want to use PSoC5 and not PSoC5LP. I have some 'defines in my code that I assume defines which devices I am targetting: 'define CYDEV_CHIP_MEMBER_5A 3 'define CYDEV_CHIP_MEMBER_5B 2 'define CYDEV_CHIP_MEMBER_USED 2 More searching suggests that CYDEV_CHIP_MEMBER_5A = PSoC5 and CYDEV_CHIP_MEMBER_5B is PSoC5LP, and so it implies that the correct device is selected, but I can't find a description of how these should be defined, and random tweaking has not helped the situation. Any guidance on how to get DYN PI for PSoC5LP enabled or pointers to the correct documentation would be much appreciated. Regards Zig |
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CyPress AN82156有一个并行输入数据路径的例子(参见代码提供的示例5)
HTTP://www. CyPress .COM/OptoSt/Aptudio-NoSe/AN82156PSOCR-3-PSOC-4-PSO-5LP-设计PSOC-CaltoTM TM 以上来自于百度翻译 以下为原文 Cypress AN82156 has an example of the parallel input to Datapath (see example #5 in code provided) http://www.cypress.com/documentation/application-notes/an82156-psocr-3-psoc-4-and-psoc-5lp-designing-psoc-creatortm |
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nvwuwy 发表于 2018-12-10 16:53 非常感谢指针的应用笔记。我已经用过这个,过去有PI工作,但只有固定模式。也就是说,每个指令的ALU的SRCA输入总是PI。 在CFG15—14中的DYN PI位应该允许每个单独的指令选择SRCA是否来自PI或A0寄存器,并且这是我的设计需要的这个特性。 我引用的链接表明,Dyn PI不适用于PSoC5,但应该适用于PSoC3和PSoC5LP。遗憾的是,DYN-PI选项似乎在数据路径工具中变灰了,并且我认为这是因为工具相信我的设计可以针对PSoC5设备。我想弄清楚如何克服这个问题。 再看一下我的代码,我看到我所说的定义只是为了仿真而实现的,所以理论是一个“红鲱鱼”。 有谁能确认他们在PSOC5LP上工作吗? 多谢。 以上来自于百度翻译 以下为原文 Many thanks for the pointer to the app note. I have already used this and have had PI working in the past, but only in fixed mode. That is to say that the SRCA input to the ALU is always PI for every instruction. The DYN PI bit in CFG15-14 should allow each individual instruction to choose whether SRCA comes from the PI or A0 register, and it is this feature that I need for my design. The link that I referenced indicates that DYN PI does not work for PSoC5 but should for PSoC3 and PSoC5LP. Sadly, the DYN PI option appears to be greyed out in the Datapath Tool, and I assume this is because the tool believes that my design may be targeted at a PSoC5 device. I'm trying to figure out how to overcome this. Looking at my code again, I see that the 'defines that I mentioned are only implemented for simulation, so that theory is a red herring. Can anyone confirm that they have DYN PI working on PSoC5LP? Many Thanks. |
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lulijian 发表于 2018-12-10 17:09 好吧,我想我只是找到了答案,以防它对其他人有帮助。 如果PiDyn位在数据路径工具中被灰色化,然后右击灰色框,您就可以选择“启用位”。这导致PI DYN比特变得可用,并且PI SEL比特随后变为灰色(因为这些选项是互斥的)。 感谢任何关注这个问题的人。 当做 以上来自于百度翻译 以下为原文 OK, I think I have just found the answer just in case it helps anyone else. If the PI DYN bit is greyed out in the Datapath Tool, then right click on the grey box and you are given the option to "Enable Bit". This results in the PI DYN bit becoming available, and the PI SEL bit then becomes greyed (as these options are mutually exclusive). Thanks for anyone that has looked into this problem. Regards |
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