哪些IRQ标志会自动清除？

你好，
似乎没有准备好的文件。与此主题相关的文档将是下面的，但是找不到直接表来回答这些问题中的查询：
PSOC5LP体系结构TRM（中断控制器章节）：HTTP://wwwyCysP.COM/FIL/123561/1下载
AN54060-PSoC 3和PSoC 5LP中断：HTTP://wwwyCysP.COM/FIL/44 256/下载
AN90799—PSoC 4中断：HTTP://wwwyCysP.COM/FIL/127121下载
PSoC Creator中断组件（ISR）数据表：HTTP://wwwyCysP.COM/FIL/13097 6/下载
至于PSoC的ARM内核，对于所有中断，中断组件的状态在ISR运行时自动清除，如上面的PSoC5LP TRM的第76页所述：
“中断条目（IRA））- CPU确认中断条目。同一中断行中的下一个断言只能在中断条目之后检测。在此之前的任何断言都被忽略了。中断控制器在收到确认后清除未决位。
但是，ARM内核中的中断是由PSOC组件的中断状态或信号边缘触发的。因此，您可能感兴趣的是了解PSoC组件需要清除中断源，以防止中断无限执行。
正如在CysISR组件数据表中所说的，在“ISRXCysPungIn（）”API描述下：
“一些中断源在读取时是清晰的，并且需要用适当的块API（GPIO、UART等）读取/清除块中断/状态寄存器。否则，ISR将继续处于未决状态，即使中断本身使用此API被清除。
可能有助于理解AN5460中“3.1中断组件配置”部分中的派生/上升沿/电平中断信号。
然后，您也可以检查组件数据表（其组件的“中断”信号，您挂钩到项目示意图中的ISR组件），以便API中断中断或状态，例如“pWMLRealStaseRealSt登记”或“PixCueStult”。
谢谢和问候，
普雷姆赛



     以下为原文
  Hi,
 
There does not seem to be a ready document for this. The documents related to this topic would be the below, but could not find a direct table answering the query in these:
 
The PSoC5LP Architecture TRM(Interrupt Controller chapter): http://www.cypress.com/file/123561/download
AN54460 - PSoC 3 and PSoC 5LP Interrupts: http://www.cypress.com/file/44256/download
AN90799 - PSoC 4 Interrupts: http://www.cypress.com/file/127121/download
PSoC Creator Interrupt component(isr) datasheet: http://www.cypress.com/file/130976/download
 
As for the ARM Core in PSoC, for all interrupts, the interrupt component's status gets cleared automatically when the isr runs, as said in page 76 of the above PSoC5LP TRM:
"Interrupt Entry (IRA) – The CPU acknowledges the interrupt entry. The next assertion in the same interrupt line can be detected only after the interrupt entry. Any assertions before that are ignored. The interrupt controller clears the pending bit upon receiving the acknowledgement."
 
But the interrupts in the ARM core are triggered by the interrupt statuses or signal edges of the PSoC components. So, you are probably interested in knowing what PSoC components need clearing of the interrupt source, to prevent the interrupts from executing infinitely.
As said in cy_isr component datasheet, under "ISR_ClearPending()" API description:
"Some interrupt sources are clear-on-read and require the block interrupt/status register to be read/cleared with the appropriate block API (GPIO, UART, and so on). Otherwise the ISR will continue to remain in pending state even though the interrupt itself is cleared using this API."
 
What may help is an understanding of the derived/rising edge/level interrupts signals in section "3.1 Interrupt Component Configuration" in the AN54460.
 
And then you may also check the component datasheets (of the components whose "interrupt" signals you are hooking to an isr component in the project schematic) for APIs to clear the interrupt or status such as "PWM_ReadStatusRegister", or "Pin_ClearInterrupt".
 
Thanks & Regards,
Prem Sai