必须为opt_design定义此单元格的内容才能成功完成

@rohithraj，
在实例化部分中缺少Component中提到的一些端口。
请检查并纠正它们。
其中很少是：
data_count：OUT STD_LOGIC_VECTOR（3 DOWNTO 0）; rd_data_count：OUT STD_LOGIC_VECTOR（3 DOWNTO 0）; wr_data_count：OUT STD_LOGIC_VECTOR（3 DOWNTO 0）; prog_full：OUT STD_LOGIC; prog_empty：OUT STD_LOGIC; ***iterr：OUT STD_LOGIC; dbiterr：OUT STD_LOGIC;
m_aclk：IN STD_LOGIC; s_aclk：IN STD_LOGIC; s_aresetn：IN STD_LOGIC; m_aclk_en：IN STD_LOGIC; s_aclk_en：IN STD_LOGIC;
--Syed
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-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
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在原帖中查看解决方案



以下为原文

@rohithraj,

Some of the ports mentioned in Component are missing in instantiation section. Please check and correct them.
Few of them are:
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
***iterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
 
--Syed
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你好@ rohithraj
从2013.3迁移到2017.4是一个巨大的Vivado版本更改（几乎8个主要的Vivado版本之间）。
有许多IP已经停止并从IP目录中删除。
合成阶段是否有与黑匣子有关的重要警告？
您需要检查您在Vivado 2013.3版本中使用的每个IP是否仍在Vivado 2017.4版本中继续使用。
问候
罗希特
RegardsRohit -------------------------------------------------
---------------------------------------------请注意 - 请注明
答案为“接受为解决方案”，如果提供的信息是有帮助的。给予您认为有用并回复导向的帖子。感谢K--
--------------------------------------------------
----------------------



以下为原文

Hi @rohithraj
 
Migrating from 2013.3 to 2017.4 is a huge Vivado version change( almost 8 major Vivado versions between). There are many IPs which has been discontinued and removed from IP catalog.
Are there any critical warnings in the synthesis phase related to black box? You need to check each IP which you used in Vivado 2013.3 version whether they are still continued in Vivado 2017.4 version.
 
Regards
Rohit
Regards
Rohit
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你好@ thakurr
没有与黑匣子相关的严重错误
以下是Synthesis中的严重错误。
[Vivado 12-4739] set_clock_groups：找不到'-group [get_clocks -include_generated_clocks {vita_clk vita_ser_clk}]'的有效对象。
[ “C：/FMC_IMAGEON/2013_3/constraints/zedboard_fmc_imageon_vita_passthrough.xdc”：141]
[Vivado 12-4739] set_clock_groups：找不到'-group [get_clocks {clk_fpga_1 clk_fpga_2}]'的有效对象。
[ “C：/FMC_IMAGEON/2013_3/constraints/zedboard_fmc_imageon_vita_passthrough.xdc”：141]
[Vivado 12-4739] set_clock_groups：找不到'-group [get_clocks clk_fpga_0]'的有效对象。
[ “C：/FMC_IMAGEON/2013_3/constraints/zedboard_fmc_imageon_vita_passthrough.xdc”：141]
实际上，我试图在Vivado 2017.4中从零开始构建这个设计，方法是在另一台PC上使用Vivado 2013.3中的设计。
[没有在Vivado 2017.4中打开Vivado 2013.3设计]
我刚从Vivado 2013复制了IP文件夹
最好的祝福，
Rohith



以下为原文

Hi @thakurr
 
There are no Critical error related to Black box 
 
Below are critical error in Synthesis. 
[Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -include_generated_clocks {vita_clk vita_ser_clk}]'. ["C:/FMC_IMAGEON/2013_3/constraints/zedboard_fmc_imageon_vita_passthrough.xdc":141][Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks {clk_fpga_1 clk_fpga_2}]'. ["C:/FMC_IMAGEON/2013_3/constraints/zedboard_fmc_imageon_vita_passthrough.xdc":141][Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks clk_fpga_0]'. ["C:/FMC_IMAGEON/2013_3/constraints/zedboard_fmc_imageon_vita_passthrough.xdc":141]Actually I tried to build this design from scratch in Vivado 2017.4 itself by having the design in Vivado 2013.3 in another PC. 
[Didn't open the Vivado 2013.3 design in Vivado 2017.4] 
 
I just copied the IP folder from Vivado 2013
 
 
Best regards, 
Rohith 
 
 

你好@ rohithraj
你能尝试在2013.3到2017.4直接迁移项目吗？
将IP文件夹从一个目录复制到另一个目录时看起来有些问题。
问候
罗希特
RegardsRohit -------------------------------------------------
---------------------------------------------请注意 - 请注明
答案为“接受为解决方案”，如果提供的信息是有帮助的。给予您认为有用并回复导向的帖子。感谢K--
--------------------------------------------------
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以下为原文

Hi @rohithraj
 
Can you try directly migrating the project in 2013.3 to 2017.4? Looks like some issue when you copy IP folder from one directory to another.
 
Regards
Rohit
Regards
Rohit
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你好@ thakurr
我试图在Vivado 2017.4中打开Vivado 2013.3设计。
我做了报告IP状态，重置输出产品和生成输出产品。
合成很好但不是实施。
有5个错误，如下所示



以下为原文

Hi @thakurr
 
I tried to open Vivado 2013.3 design in Vivado 2017.4.
I did the report IP status, reset output products and generate output products.
Synthesis was good but not Implementation.
 
 
Having 5 errors as shown below
 
 
 

@rohithraj，
您是否在升级IP日志中看到任何警告？
检查IP的实例化模板文件。
在设计中使用它时，请确保它匹配。
您是否能够在源窗口下看到层次结构中的IP？
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------



以下为原文

@rohithraj,
 
Did you see any warning in upgrade IP log? Check the instantiation template file of the IP. Make sure it matches when you are using it in your design. 
 
Are you able to see the IP in hierarchy under sources window?
 
--Syed
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你好@ syedz
IP升级时我没有看到任何警告。
但是当我看到层次结构时，FIFO就是问题，如下所示。
我认为这是因为Vivado 2017.4中没有fifo_generator_v11_0。
所以我回到IP脚本文件，改变它到处都是fifo_generator_v13_2。
[猜猜升级IP无法做到，所以我手动完成了]
即使在此脚本更改后，我也会得到相同的opt_design ERROR / Black框错误，层次结构中FIFO的问号图标
脚本更改后的层次结构。
注意：一切都在Vivado 2017.4中运行
最好的祝福，
Rohith



以下为原文

Hi @syedz
 

• I didn´t see any warning while IP upgrades. 
  

 

• But when I see in hierarchy, FIFO were the issue as shown below. 
  

 
 

• I thought this was because fifo_generator_v11_0 is not available in Vivado 2017.4.  
  

 

• So I went back to the IP script file changed it fifo_generator_v13_2 everywhere. 
  

     [Guess Upgrade IP couldn´t do it, so I did it manually] 
 
 
 
 
 

• Even after this script change, I get the same opt_design ERROR/ Black box error, Question mark icon for FIFO in hierarchy 
  

 

• Hierarchy after script change. 
  

 

 
Note: Everything running in Vivado 2017.4
 
Best regards, 
Rohith
 

你好@ rohithraj
您可以尝试从设计层次结构中删除IP文件design_1_fmc_imageon_vita_receiver_0_0.xci文件吗？
现在，在生成输出产品后，再将此IP从Vivado 2017.4的IP目录添加到项目中。
问候
罗希特
RegardsRohit -------------------------------------------------
---------------------------------------------请注意 - 请注明
答案为“接受为解决方案”，如果提供的信息是有帮助的。给予您认为有用并回复导向的帖子。感谢K--
--------------------------------------------------
----------------------



以下为原文

Hi @rohithraj
 
Can you try deleting IP file design_1_fmc_imageon_vita_receiver_0_0.xci file from the design hierarchy? Now add this IP from the IP catalog of Vivado 2017.4 to the project again once you generate the output products.
 
Regards
Rohit
Regards
Rohit
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你好@ thakurr
当我右键单击design_1_fmc_imageon_vita_receiver_0_0.xci文件时，没有删除或删除选项。
[删除项目中的文件已禁用]
BR / Rohith



以下为原文

Hi @thakurr
 
When I right click the design_1_fmc_imageon_vita_receiver_0_0.xci file, there is no option to remove or delete. [Remove file from project is disabled]
 
BR/ Rohith 

@rohithraj，
我认为实例化中使用的IP名称和名称仍然存在一些不匹配。
你能复习一下吗？
也可以尝试直接添加文件。
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------



以下为原文

@rohithraj,

I think there is still some mismatch in the name of the IP and name used in the instantiation. Can you please recheck this? 
Also try adding the file directly.
 
--Syed
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你好@ syedz
即使我有同样的感受。
我认为它是因为FIFO vhd文件的实例化，如版本，库
你能看看封装的FIFO文件吗？
BR / Rohith
afifo_32.zip 4 KB



以下为原文

Hi @syedz
 
Even I feel the same. 
 
I think its because of the instantiation of FIFO vhd file like version, library 
 
Could you please have a look at FIFO file enclosed ? 
 
BR/ Rohith
 
            afifo_32.zip ‏4 KB

@rohithraj，
在实例化部分中缺少Component中提到的一些端口。
请检查并纠正它们。
其中很少是：
data_count：OUT STD_LOGIC_VECTOR（3 DOWNTO 0）; rd_data_count：OUT STD_LOGIC_VECTOR（3 DOWNTO 0）; wr_data_count：OUT STD_LOGIC_VECTOR（3 DOWNTO 0）; prog_full：OUT STD_LOGIC; prog_empty：OUT STD_LOGIC; ***iterr：OUT STD_LOGIC; dbiterr：OUT STD_LOGIC;
m_aclk：IN STD_LOGIC; s_aclk：IN STD_LOGIC; s_aresetn：IN STD_LOGIC; m_aclk_en：IN STD_LOGIC; s_aclk_en：IN STD_LOGIC;
--Syed
--------------------------------------------------
-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
--------------------------------------------------
-------------------



以下为原文

@rohithraj,

Some of the ports mentioned in Component are missing in instantiation section. Please check and correct them.
Few of them are:
data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
***iterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
 
--Syed
---------------------------------------------------------------------------------------------
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你好，你通过完成这些端口分配解决了这个问题？
我正在尝试将此IP内核升级到Vivado 2017.2，但仍然会出现同样的错误。



以下为原文

Hello did you solve this problem by completing these ports assignment?
I am trying to upgrade this ip core into Vivado 2017.2, but still get the same error.