FPGA编辑器中的块层次结构不正确

你好@ hanieh_jafarzadeh，
当我在FPGA编辑器中添加一个组件时，我会添加comp，然后在其中进行路由，然后将外部部分路由到最后。
在某些情况下，comp内部有多个路径，因此系统不知道选择哪个路径。
祝你好运，
克里斯
在原帖中查看解决方案



以下为原文

Hello @hanieh_jafarzadeh,
 
When I would add a component inside FPGA Editor, I would add the comp, and then route inside of it, and then route the outside portion last.  In some situations, there are multiple paths inside the comp, so the system does not know which one to select.  
 
Good Luck,
Chris
View solution in original post

您能说明添加组件并建立连接所遵循的步骤吗？
我建议您选择引脚和现有网络，然后单击“添加”按钮。
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-----------------------不要忘记回答，kudo，并接受为解决方案.-------------
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以下为原文

Can you illustrate the steps you followed to add the component and make the connection?
I'd suggest that you select the pin and the existing net, then click Add button.
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Don't forget to reply, kudo, and accept as solution.
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你好@ hanieh_jafarzadeh，
添加COMP之后，您是否手动在COMP内部路由？ 
在SLICE / CLB COMP内部，您必须将时钟和其他信号路由到其中。
祝你好运，克里斯



以下为原文

Hello @hanieh_jafarzadeh,
 
After you added the COMP, did you manually route inside of the COMP?
  Inside the SLICE/CLB COMP, you must route the clock and other signals inside of it.
 
Good Luck,
Chris

Dearchrisz
根据教程，“当一个输入引脚（净负载）被自动路由时，引脚和网络驱动器之间的连接被路由”，所以我为组件的输入引脚启用了这个选项，连接到的网络
它以及组件。
我从未使用FPGA编辑器手动路由，我是否需要在COMP内部手动路由，尽管我已启用此选项？
我还实施了其他人在论坛中建议的解决方案，例如：
- 使用-ignore_keep_hierarchy选项运行Map
- 设置以下环境变量：
SET XIL_MAP_DISABLE_KH_NO_CLIP = 1
- 锁定目标网络的路由
但错误仍然存​​在



以下为原文

 
Dear chrisz
  according to the tutorial, " When an input pin (a net load) is automatically routed, the connection between the pin and the net driver is routed ", so I enabled this option for my input pin of component, the net that is connected to it and also the component. 
I have never used FPGA Editor manual routing, do I need to manually route inside of the COMP although I have enabled this option?
I also implemented this solutions that others had suggested in the forum such as :
- run Map  with the -ignore_keep_hierarchy option
- setting the following environment variable:
SET XIL_MAP_DISABLE_KH_NO_CLIP=1
- Lock the routing of the intended net 
 
but the error still exists 
 

你好@ hanieh_jafarzadeh，
当我在FPGA编辑器中添加一个组件时，我会添加comp，然后在其中进行路由，然后将外部部分路由到最后。
在某些情况下，comp内部有多个路径，因此系统不知道选择哪个路径。
祝你好运，
克里斯



以下为原文

Hello @hanieh_jafarzadeh,
 
When I would add a component inside FPGA Editor, I would add the comp, and then route inside of it, and then route the outside portion last.  In some situations, there are multiple paths inside the comp, so the system does not know which one to select.  
 
Good Luck,
Chris

你是对的。
我做了组件的内部路由，现在修复了错误。谢谢你的回复



以下为原文

You are right.
I did the inside routing of the component and now the error is fixed.
thanks a lot for your reply
 

亲爱的@青睐
我完全做了这些步骤，但我完全忘记了组件的内部路由。
我做到了，现在错误已修复。
非常感谢您的回复



以下为原文

Dear @graces
I exactly did these steps but I totally forgot about inside routing of the component.
I did it and now the error is fixed.
thanks a lot for your reply 

@hanieh_jafarzadeh，
谢谢你的更新。
您能否通过标记有助于解决问题的帖子来关闭此主题“接受为解决方案”
--Syed
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-------------------------------------------请注意 - 请标记答案
如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------
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以下为原文

@hanieh_jafarzadeh,

Thanks for update. Can you please close this thread by marking the post which helped in resolving the issue with "Accept as Solution"
 
--Syed
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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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当然
完成:)



以下为原文

sure 
Done :)