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嗨,
我尝试在PYNQ板上实现HW中的矩阵乘法。 我使用HLS构建了一个IP但是当我在Vivado中使用它时,我有一些我无法解决的错误。 当我运行synth_design时,我有以下警告: 错误:[DRC INBB-3] ip中的几个DSP被认为是黑盒子。 然后设计优化失败。 我附上了一份包含我的报告的文本文件。 你能帮我解决这个问题吗? 谢谢, Kinan Al Khouja error_tcl.txt 652 KB 以上来自于谷歌翻译 以下为原文 Hi, I try to implement a matrix multiplication in HW on the PYNQ board. I have built an IP using HLS but when i use it in Vivado i have some errors i cannot resolve. When i run synth_design i have the following warning : ERROR: [DRC INBB-3] Several DSPs in the ip are considered as a blackbox. Then the design optimization fails. I have attached a text file with the reports i have. Could you help me solve this problem. Thank you, Kinan Al Khouja error_tcl.txt 652 KB |
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3个回答
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嗨@ kinan,
根据您的日志,黑盒子错误显示在opt_design阶段。 Synth_design成功通过。 看看这个帖子,这可能会帮到你。 https://forums.xilinx.com/t5/Design-Entry/quot-DRC-INBB-3-Black-Box-Instances-quot-Unable-to-instantiate/td-p/801905 问候, hemangd 以上来自于谷歌翻译 以下为原文 Hi @kinan, Based on your log, black box errors are shown in the opt_design phase. Synth_design passes successfully. Have a look into this thread, this may help you out. https://forums.xilinx.com/t5/Design-Entry/quot-DRC-INBB-3-Black-Box-Instances-quot-Unable-to-instantiate/td-p/801905 Regards, hemangd |
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以上来自于谷歌翻译 以下为原文 Sorry, didnt work. I still have problems with the floating... dsp thing. Sometimes is a critical warning about a black box for design_1 but again when I tried to synth design floating ... dsp as IP (top) and when back to design_1 as top again. Please, see the full sequences (tcl_out + vivado log), that is the only thing I can send you. There is another error message when I tried to do archive project. Can you help us? *****here some warnings: synth_design Command: synth_design Starting synth_design Using part: xc7z020clg400-1 WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_targsynth_design Command: synth_design Starting synth_design Using part: xc7z020clg400-1 WARNING: [Vivado_Tcl 4-393] The 'Synthesis' target of the following IPs are stale, please generate the output products using the generate_target or synth_ip command before running synth_design. c:/Users/Researcher/matrimult/solution1/impl/ip/tmp.srcs/sources_1/ip/matrixmul_accel_core_ap_fadd_3_full_dsp_32/matrixmul_accel_core_ap_fadd_3_full_dsp_32.xci WARNING: [IP_Flow 19-2162] IP 'matrixmul_accel_core_ap_fadd_3_full_dsp_32' is locked: * IP definition 'Floating-point (7.1)' for IP 'matrixmul_accel_core_ap_fadd_3_full_dsp_32' (customized with software release 2016.1) has a different revision in the IP Catalog. * Current project part 'xc7z020clg400-1' and the part 'xc7vx485tffg1157-1' used to customize the IP 'matrixmul_accel_core_ap_fadd_3_full_dsp_32' do not match. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more *****here more critical warnings (same problem): 63 instances of this cell are unresolved black boxes. [c:/Users/Researcher/project_5/project_5.srcs/sources_1/bd/design_1/ipshared/7353/hdl/ip/matrixmul_accel_core_ap_fadd_3_full_dsp_32.vhd:198] CRITICAL WARNING: [Project 1-560] Could not resolve non-primitive black box cell 'design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__design_1_matrixmul_accel_core_0_0__floating_point_v7_1_2_0' instantiated as 'design_1_i/matrixmul_accel_core_0/inst/matrixmul_accel_core_U/grp_matrixmul_accel_core_matrixmul_fu_796/matrixmul_accel_core_fadd_32ns_32ns_32_5_full_dsp_U0_0/matrixmul_accel_core_ap_fadd_3_full_dsp_32_u/U0'. 63 instances of this cell are unresolved black boxes. [c:/Users/Researcher/project_5/project_5.srcs/sources_1/bd/design_1/ipshared/7353/hdl/ip/matrixmul_accel_core_ap_fadd_3_full_dsp_32.vhd:198] *****here more critical warnings (same problem): CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'floating_point_v7_1_2_0_HD1327' instantiated as 'design_1_i/matrixmul_accel_core_0/inst/matrixmul_accel_core_U/grp_matrixmul_accel_core_matrixmul_fu_796/matrixmul_accel_core_fmul_32ns_32ns_32_4_max_dsp_U63_0/matrixmul_accel_core_ap_fmul_2_max_dsp_32_u/U0' [c:/Users/Researcher/project_5/project_5.srcs/sources_1/bd/design_1/ipshared/7353/hdl/ip/matrixmul_accel_core_ap_fmul_2_max_dsp_32.vhd:198] tcl_out.txt 1934 KB vivado.log 4 KB |
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嗨@ kinan,
我在这里可以看到两个问题: >> * IP定义'浮点(7.1)'用于IP'matrixmul_accel_core_ap_fadd_3_full_dsp_32'(用软件版本2016.1定制)在IP目录中有不同的版本。>> *当前项目部分'xc7z020clg400-1'和部分'xc7vx485tffg1157 -1'用于自定义IP'matrixmul_accel_core_ap_fadd_3_full_dsp_32'不匹配。 您可以通过应用tcl命令report_ip_status来检查它。 1.通过应用tcl命令升级您的IP:upgrade_ip [get_ips {}] 2.使用升级流程更改项目部件或将此IP重新定位到当前项目部件或板。 然后重置并重新生成输出产品并检查。 问候, hemangd 以上来自于谷歌翻译 以下为原文 Hi @kinan, Two issues i can see here: >>* IP definition 'Floating-point (7.1)' for IP 'matrixmul_accel_core_ap_fadd_3_full_dsp_32' (customized with software release 2016.1) has a different revision in the IP Catalog. >> * Current project part 'xc7z020clg400-1' and the part 'xc7vx485tffg1157-1' used to customize the IP 'matrixmul_accel_core_ap_fadd_3_full_dsp_32' do not match. You can check it by applying tcl command report_ip_status. 1. Upgrade your IP by applying tcl command: upgrade_ip [get_ips { 2. Change the project part or re-target this IP using the upgrade flow to the current project part or board. Then reset and regenerate the output products and check. Regards, hemangd |
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