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我还在研究我的频率计数器,注意到TCPWM计数器有一些奇怪的问题。似乎我无法通过来自UDB细胞的信号来启动/停止它(我使用DFFs在那里)。我也有问题通过门和门控计数信号。
见附上的项目-它基本上是自包含的,但需要一个诺基亚5110连接(但它可以取代通过发送一个串行端口的结果)。 这实现了一个倒数频率计数器。它使用两个类似的计数器(具有24位周期)。它们从输入信号的第一下降沿开始,计数器等待直到参考计数器第一次溢出。当这种情况发生时,输入信号的下一个下降沿停止两个计数器。然后,可以使用参考值和输入计数器的计数值来计算输入频率。 为了开始测量CycLy,使用一个控制寄存器,它重置DFFS并重新加载计数器(通过‘1’脉冲’)。 由于PSoC6的TCPWMs没有启用信号(如PSOC4中的),所以我使用启动和停止输入。启动信号上的上升侧(来自3输入和)启动计数器,下降沿停止计数器。此外,下降沿捕获当前计数器值。 我观察到的是: 即使计数器被停止,它们看起来还要计数-读取当前计数器值,并将它们与捕获值进行比较,显示差异(不应该是计数器停止后)。一个与门(使用启用信号)。当这样做时,计数器不计数。在某些低输入频率下,输入计数器不重新加载,但保持其当前值(可以看到,因为显示实际计数器值,而输入值正好在其他低输入频率上),输入计数器溢出A。当它开始时(代码显示为“频率太高”),最后一个可能是由第三个引起的,但是一到三个问题非常令人费解。特别是数字2——这很简单,我认为一个人不能做错任何事,但它不起作用。 我观察这个行为,不管代码运行的核心是什么。我有一个版本在M0上运行,一个版本是M4,一个是代码被拆分的版本。后者似乎是最差的,从我在调试过程中发现的,这似乎是因为完成一次测量和下一次测量之间的延迟在这里是最短的。 我还试图通过使用SyStReTo()函数重置计数器,但这似乎完全打破了它们。 你知道我做错什么了吗? 谢谢, HLI NoKiaLy0.0.Cyrj.CaseVo.01.Zip 1.6兆字节 以上来自于百度翻译 以下为原文 I'm still working on my frequency counter, and noticed some strange issues with the TCPWM counter. It seems I cannot start / stop it properly via signals coming from the UDB cells (I'm using DFFs there). I also had problems gating the count signal via an AND gate. See the attached project - it is basically self-contained, but needs a a Nokia 5110 connected (but it could be replaced by sending the results via a serial port). This implements a reciprocal frequency counter. It uses two similar counters (with 24 bit period). They are started with the first falling edge of the input signal, and the the counter waits until the reference counter overflows for the first time. When this happens, the next falling edge of the input signal stops both counters. Then one can use the count values of the reference and the input counter to calculate the input frequency. To start a measurement cycly, a control register is used which resets the DFFs and reloads the counters (by a '1' pulse). Since the TCPWMs of PSoC6 do not have an enable signal (as there was in the PSoC4), I'm using the start and stop inputs. A rising flank on the enable signal (which comes from the 3-input AND) starts the counters, and the falling edge stops the counters. Also, the falling edge captures the current counter values. What I observe is:
I observer this behaviour regardless of the core the code is running. I have one version of that running on the M0, one with the M4 and one where the code is split. The latter one seems to be the worst, from what I have found out during debugging this seems to be because the delay between finishing one measurement and starting the next is the shortest here. I also tried to reset the counters by using the _SetCounter() function, but this seems to completely break them. Any idea what I'm doing wrong here? Thanks, hli |
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我快速浏览了一下你的项目。首先我要注意的是,开始、停止和捕获输入都是连接在一起的。看TRM,它表明,如果一个开始和停止同时发生,停止有更高的优先级,所以开始忽略。重新加载确实重新加载并启动计数器,所以也许您不需要启动输入连接,只是重新加载。你想用开始做某事吗?或者只是不希望你的示意图上有任何未连接的节点。
至于你关于启用信号的评论,我不确定我是否理解。PSoC 4中的TCPWM计数器没有启用,也许您指的是UDB计数器。不管怎样,你都可以把计数输入看作是使能。计数输入工作的方式是,当计数输入很高时,计数器将计数时钟输入的上升沿。换句话说,计数器在计数输入高时计数时钟输入的每一个上升沿。 CE220692提供了一种使用TCPWM测量频率的方法。我会推荐类似于这个例子中所示的东西。只需替换PWM以产生不同频率的输入。 以上来自于百度翻译 以下为原文 I did a quick look at your project. First thing that stands out to me is that the start, stop and capture inputs are all connected together. Looking at the TRM it indicates that if a start and a stop occur at the same time the stop has higher priority so the start is ignored. A reload does reload and start the counter, so maybe you don't need to start input connected, just the reload. Were you wanting to use the start for something? Or just not wanting any unconnected nodes on your schematic. As for you comment about the enable signal I'm not sure I understand. The TCPWM counters in PSoC 4 don't have an enable maybe you are referring the UDB counters. Regardless you can think of the count input as the enable. The way the count input works is that when ever the count input is high the counter will count on a rising edge of the clock input. To say it another way the counter counts each rising edge of the clock input when the count input is high. CE220692 provides a method for measuring the frequency using a TCPWM have you looked at that. I would recommend something similar to what is shown in that example. Just replace the PWM for generating different frequencies with your input. |
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60user133 发表于 2018-11-2 12:42 CE220692采用门计数法进行测量。使用这种方法精度较低,频率较低,这就是为什么我想使用倒数计数。 是的,启动和停止连接在一起,但在上升沿启动触发器,并在下降沿停止。所以它们永远不会同时触发。两个输入都连接到一个信号(应该标记为“启用”),它决定计数器何时需要运行。我可以把它拆开,因为它实际上是从一个开始和几个停止事件计算出来的。 关于启用信号:您是正确的,这在PSOC4 TCPWM中不存在。我混淆了PSOC5的基于UDB的计数器(这是我原来的项目)。 但是你的观察,重新加载事件也开始计数器实际上可能是罪魁祸首。它至少可以解释我的一些观察结果。我将尝试使用ReLoad,而不是今晚开始,看看会发生什么。 我现在有点困惑如何计数器实际上工作。从你所写的看来,它计数计数时钟输入时,计数为“1”。我真正想要的是计数计数输入(或上升沿)的计数输入。TRM只是说 计数器功能在“活动计数”预分频时钟上执行,时钟由“计数事件”信号控制。例如,计数器每计数一个计数器周期递增或递减“1”,其中计数事件被检测到。 这就意味着什么是“计数事件”。我已经配置了计数为“上升沿”,因为我认为这就是我所需要的。CE220692也以这种方式工作(当‘计数’将作为‘时钟’的启用信号时,它将不能正常工作。事实上,输入频率根本不影响捕获值,假设占空比为50%)。 以上来自于百度翻译 以下为原文 CE220692 does measurement by the gate-counting method. Using the means accuracy gets lower with lower frequencies - thats why I wanted to use reciprocal counting. Yes, start and stop are connected together, but start triggers on a rising edge and stop on a falling edge. So they will never be triggered at the same time. Both inputs are connected to a signal (which should be labelled 'enable') which determines when the counters need to run. I could look into splitting this up since its actually calculated from a start and several stop events. Regarding the enable signal: you are right, this does not exist in the PSoC4 TCPWM. I confused that with the UDB-based counter of the PSoC5 (which was my original project). But your observation that the reload event also starts the counter might actually be the culprit. It would explain at least some of my observations. I will try to to use reload instead of start this evening and see what happens. I'm a little bit confused now how how the counter actually works. From what you wrote it seems it counts pulses from the clock input when count is '1'. What I actually want is to just count pulses (or rising edges) on the count input. The TRM just says [size=15.0163px]The counter functionality is performed on an “active count” prescaled clock, which is gated by a “count event” signal. For example, a counter increments or decrements by ‘1’ every counter clock cycle in which a count event is detected. [size=15.0163px]which leaves the question what a 'count event' is. I have configured the count to 'rising edge' because I thought that's what I need. CE220692 also works that way (it would not work correctly when 'count' would act as an enable signal for 'clock' - in fact then the input frequency should no influence the captured value at all, assuming a 50% duty cycle). |
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60user133 发表于 2018-11-2 12:42 另外一个注意事项:不能将外部信号连接到TCPWM时钟的输入端。我发现时钟输入可以被配置为“level”,这使得它像一个启用信号(我以前使用‘上升沿’)。但是时钟信号实际上必须来自时钟块。它甚至不可能使用来自外部数字信号的时钟(至少我没有这样做的成功)。 使用“重新加载”作为启动信号没有解决问题。有效的方法是禁用“重新加载”输入,并在软件中重新加载(使用SETUROR())。但是,输入计数器似乎没有正确捕获,也没有正确地停止(ReffCad行为良好,并且两者都配置相同)。 以上来自于百度翻译 以下为原文 An additional note: one cannot connect an external signal to the TCPWM 'clock' input. I found out that the clock input can be configured to 'level', which makes it act like an enable signal (I used 'rising edge' before). But the clock signal must actually come from the clock block. Its not even possible to use a clock derived from an external digital signal (at least I had no success in doing so). Using 'reload' as a start signal did not work out. What works is to disable the 'reload' input, and do the reload in software (with SetCounter()). But still the InputCounter does not seem to capture properly, nor does it stop properly (the RefCounter behaves fine, and both are configured identically). |
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