完善资料让更多小伙伴认识你，还能领取20积分哦， 立即完善>
3天内不再提示
电子发烧友论坛
1844
|
我对Vivado工具如何决定如何映射（例如，从GPIO外部制作的“led”端口到实际引脚而不指定XDC文件中的名称感到困惑。
在我看来，只要指定一个引脚，vivado就会以某种方式将一个阵列中的所有端口猜测并匹配到实际电路板上正确的PIN / IOSTANDARD。 如您所知，文档数量巨大。 你能指点我正确的文件（或视频）来一劳永逸地解决这些疑惑吗？ 我通过反复试验逃脱了它，但我想最终深入理解它。 谢谢。 以上来自于谷歌翻译 以下为原文 I am sort of confused with how Vivado tools decide how to map, for example, a "led" port made external from GPIO to the actual pins without specifying the name in a XDC file. Also it seems to me that vivado will somehow guess and match all ports in one array to the proper PIN/IOSTANDARD on the actual board with just specifying one pin. As you know the number of docs is huge. Can you point me to the proper doc (or video) to get through these doubts once and for all? I have been getting away with it by trial and error but I want to finally understand it in depth. Thank you. 
0
|
|
相关推荐
2个回答
|
|
|
@ubenevides那是因为你正在使用电路板的流程，并且有一个单独的电路板xdc文件，该工具将读取并分配位置和IO标准。
我在下面的帖子中用一个例子解释了这一点。 https://forums.xilinx.com/t5/Embedded-Processor-System-Design/UG-940-Where-is-the-board-XDC-brought-into-the-tutorial/td-p/659586 -Pratham ------------------------------------------------ ----------------------------------------------请注意 - 请 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K- -------------------------------------------------- ----------------------- 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 @ubenevides That was because you are using the boards' flow and there is a separate board xdc file which tool would read and assign Location and IO standard. I have explained this with an example in the below post. https://forums.xilinx.com/t5/Embedded-Processor-System-Design/UG-940-Where-is-the-board-XDC-brought-into-the-tutorial/td-p/659586 -Pratham ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ----------------------------------------------------------------------------------------------View solution in original post |
|
|
|
|
|
@ubenevides那是因为你正在使用电路板的流程，并且有一个单独的电路板xdc文件，该工具将读取并分配位置和IO标准。
我在下面的帖子中用一个例子解释了这一点。 https://forums.xilinx.com/t5/Embedded-Processor-System-Design/UG-940-Where-is-the-board-XDC-brought-into-the-tutorial/td-p/659586 -Pratham ------------------------------------------------ ----------------------------------------------请注意 - 请 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K- -------------------------------------------------- ----------------------- 以上来自于谷歌翻译 以下为原文 @ubenevides That was because you are using the boards' flow and there is a separate board xdc file which tool would read and assign Location and IO standard. I have explained this with an example in the below post. https://forums.xilinx.com/t5/Embedded-Processor-System-Design/UG-940-Where-is-the-board-XDC-brought-into-the-tutorial/td-p/659586 -Pratham ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
|
|
|
|
只有小组成员才能发言，加入小组>>
2384 浏览 7 评论
2800 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办？
2264 浏览 9 评论
3336 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区？
2431 浏览 15 评论
有输入，但是LVDS_25的FPGA内部接收不到数据，为什么？
759浏览 1评论
请问vc707的电源线是如何连接的，我这边可能出现了缺失元件的情况导致无法供电
548浏览 1评论
求一块XILINX开发板KC705，VC707，KC105和KCU1500
371浏览 1评论
1966浏览 0评论
685浏览 0评论
/6 
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 （电路图） 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证：合字B2-20210191
工商网监
湘ICP备2023018690号
评论
淘帖
2218
