怎么从报告中找出时钟速度

路易斯，
在这种情况下，CCLK（配置时钟）的源头，您提供的内容或您指示的内容。
在JTAG的情况下，CCLK来自JTAG CLK。
在从机串行或从机主模式的情况下，它是您连接到CCLK引脚的时钟。
在主模式的情况下，它是您选择的内部时钟（默认或选项）。
什么设备系列？
知道这一点，数据表将提供CCLK内部费率（rangle）。
您的原理图（或您的电路板 - 它是可用的演示板之一吗？）将显示是否有外部振荡器连接到CCLK引脚。
最后，如何设置模式引脚将决定模式（哪个时钟），并且比特流中的选项可能选择除内部默认频率之外的其他选项。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Luis,
 
In this case, the CCLK (configuration clock) has at its source, what you have provided it with, or what you have directed it to be.

In the case of JTAG, the CCLK is derived from the JTAG CLK.

In the case of slave serial, or slave master modes, it is the clock you have attached to teh CCLK pin.

In the case of master modes, it is the internal clock you have selected (either the default, or an option).
 
What device family?  Knowing that, the data sheet will provide the CCLK internal rate (rangle).  Your schematic (or your board -- is it one of the available demo boards?) will then show if there is an external oscillator attached to the CCLK pin.
 
Finally, how the mode pins are set will determine the mode (which clock), and the options in the bitstream may be selecting something other than the internal default frequency.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

对不起，该设备是Virtex II Pro。事实上，我没有写这个设计，我从来没有见过它。
有一些保密问题......我所拥有的只是ISE软件生成的报告。



以下为原文

Sorry, the device is Virtex II Pro.
As a matter of fact, I did not write this design, and I have never even seen it. There are some confidentialty issues... All I have is the reports generated by the ISE software.

路易斯，
比描述设计的文件更重要的是电路板的原理图，以及它是如何连接的。
设置了什么模式？
（如何连接模式引脚）
是否有时钟源连接到CCLK引脚？
回答这两个问题，你会知道接下来要做什么。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Luis,
 
More important than the files descrbing the design, is the schematic of the board, and how it is wired.
 
What mode is set?  (how are the mode pins wired)
 
Is there a clock source connected to the CCLK pin?
 
Answer those two questions and you will know what to go do next.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

您对FPGA的配置方式或设计的时钟速度感兴趣吗？
在FPGA领域，当我们说“配置”时，这是FPGA从某些非易失性存储器加载其bistream的过程。
奥斯汀的答案都假设您正在使用具有该含义的“已配置”一词。
但是，如果您试图找出设计的时钟速度，那么答案就会有所不同。
您的设计速度取决于电路板上的振荡器，该振荡器驱动FPGA的（可能是几个）时钟。
如果FPGA正确实现并设计为与该板一起使用，则在构建FPGA比特流时，这些时钟所强加的要求（以及一大堆其他物理约束）通过约束传递给工具。
再次，假设FPGA正确实现，设计应该能够满足这些约束，因此唯一（真正有意义的）答案是“无论板上的时钟是什么”。
但是，您可以（间接）在“约束”部分中查看.par文件中应用于设计的约束。
这显示了设计的所有限制，如果它们通过或失败，以及有多少保证金。
如果您可以阅读UCF / PCF格式，您可以从中了解设计是如何受到约束的，因此在设计构建时使用了什么时钟以及它是否满足这些约束。
.par文件中的下一部分 - “派生约束报告”可能会更直接地回答您的问题;
它显示了哪些约束定义了时钟（直接或作为衍生物）所需的周期，以及它可以满足的最小周期。
但是，这只是一个总结 - 真正的要求显示在上一节中。
Avrum



以下为原文

Are you interested in how the FPGA is configured or the clock speeds of the design?
 
In the FPGA world, when we say "configuration", that is the process whereby the FPGA loads its bistream from some non-volatile memory. Austin's answers are all assuming you are using the word "configured" with that meaning.
 
If, however, you are trying to figure out the clock speed of the design, then the answer is a bit different.
 
The speed of your design is determined by the oscillator on the board that drives the (potentially several) clocks to the FPGA. If the FPGA was implemented correctly and designed to go with this board, then when the FPGA bitstream was built the requirements imposed by these clocks (and a whole bunch of other physical constraints) were communicated to the tools via constraints. Again, assuming the FPGA was implemented correctly, the design should have been able to meet those constraints, and hence the only (really meaningful) answer is "whatever the clocks on the board are".
 
However, you can (indirectly) see the constraints applied to the design in the .par file in the "Constraint" section. This shows all the constraints on the design, if they passed or failed, and how much margin there is. If you can read UCF/PCF format, from this you can figure out how the design was constrained, and therefore what clocks were used when the design was built and whether it met those constraints.
 
The next section in the .par file - the "Derived constraint report" may answer your question a little more directly; it shows which constraints define clocks (directly or as a derivative) what period is required, and what the smallest period it could meet is. However, this is just a summary - the real requirements are shown in the previous section.
 
Avrum