完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
扫一扫,分享给好友
我在vhdl中设计了一个模数(2n + 1)乘法器,带有2个设计--- 1个组合,即没有时钟和另一个流水线设计
组合电路中的综合报告如下 最短期限:未找到路径 时钟前的最小输入到达时间:未找到路径 时钟后最大输出所需时间:未找到路径 最大组合路径延迟:43.684 ns 对于流水线设计,综合报告可以找到 最小周期:2.616 ns(最大频率:382.291 MHz)时钟前的最小输入到达时间:5.016ns时钟后的最大输出所需时间:4.092ns最大组合路径延迟:未找到路径 从理论上讲,我可以证明流水线设计的吞吐量(即每单位时间处理的位数)多于组合设计的吞吐量。但是如何从综合报告中得出相同的结论呢? 在流水线设计的综合报告中,没有找到组合路径延迟,这是非常清楚的,因为没有从没有时钟的输入到输出找到路径。但是我怎样才能计算出这个设计的延迟? 是否有任何计算需要在流水线设计中找到输出延迟输入.... 以上来自于谷歌翻译 以下为原文 I have designed a modulo (2n + 1) multiplier in vhdl with 2 design--- 1 combinational i.e without clock and another pipelined design The synthesis report in combinational circuit is found as Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 43.684 ns For the pipelined design, the synthesis report is found as Minimum period: 2.616 ns (Maximum Frequency: 382.291 MHz) Minimum input arrival time before clock: 5.016ns Maximum output required time after clock: 4.092ns Maximum combinational path delay: No path found Theoretically I can prove that the throughput( i.e the number of bits processed per unit time) of the pipelined design is more that that of combinational design.But how can I conclude the same thing from the synthesis report?? In the synthesis report of the pipelined design, the combinational path delay is not found which is quite clear as no path is found from input to output which do not have a clock.But how can I calculate the delay in this design? Is there any calculation need for finding input to output delay in pipelined designs....??? |
|
相关推荐
4个回答
|
|
我很困惑......你想知道输入和输出之间的延迟吗?
为此,只需将管道阶段的数量乘以最小周期即可。 或者您想计算每个设计的吞吐量? 阿德里安 请在询问之前先查询您的问题。如果有人回答您的问题,请在“接受为解决方案”标记该帖子。 如果你看到一个特别好的和信息丰富的帖子,考虑给它Kudos(左边的星)。 以上来自于谷歌翻译 以下为原文 I'm puzzeled... Do you want to know the latency between input and output? For that, just multiply the number of pipeline stages with the minium period. Or do you want to calculate the throughput of each design? Adrian Please google your question before asking it. If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left). |
|
|
|
不,我想计算设计的吞吐量。
我有比特数和频率。 以上来自于谷歌翻译 以下为原文 No I want to calculate the throughput of the design. I have the number of bits and the frequency with me. |
|
|
|
我认为这是一个家庭作业,所以我只会给你提示,而不是完整的答案。
如何定义“吞吐量”? 它的数学公式是什么? 它与单个位没有任何关系。 这有帮助吗? 请在询问之前先查询您的问题。如果有人回答您的问题,请在“接受为解决方案”标记该帖子。 如果你看到一个特别好的和信息丰富的帖子,考虑给它Kudos(左边的星)。 以上来自于谷歌翻译 以下为原文 I assume this is a homework assignment, so I'll only give you hints, not the full answer. How is "throughput" defined? What is the mathematical formula for it? It doesn't have anything to do with individual bits. Does that help? Please google your question before asking it. If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left). |
|
|
|
嘿,你找到解决这个延迟的问题的解决方案。
我也面临同样的问题请帮帮我 以上来自于谷歌翻译 以下为原文 Hey did u find solution for this problme of finding delay. Iam also facing same problem please help me |
|
|
|
只有小组成员才能发言,加入小组>>
2291 浏览 7 评论
2701 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2186 浏览 9 评论
3262 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2330 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
598浏览 1评论
1662浏览 1评论
159浏览 1评论
在使用xc5vsx95T时JTAG扫片不成功,测量TDO无信号输出
2311浏览 0评论
631浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-9-1 12:29 , Processed in 1.032753 second(s), Total 53, Slave 46 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191