完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
V5文档UG190声明如下:
单端时钟必须连接到差分全局时钟引脚的正(P)侧。 如果单端时钟连接到差分引脚对的P侧,则连接到N侧 不能用作另一个单端时钟引脚 除了P侧的单独单端时钟外,如果设计将单端时钟连接到N侧,还有什么意义呢? 这似乎违反了这条规则,但其含义是什么? 以上来自于谷歌翻译 以下为原文 V5 documentation UG190 states the following: A singleended clock must be connected to the positive (P) side of the differential global clock pins. If a single-ended clock is connected to the P-side of a differential pin pair, then the N-side can not be used as another single-ended clock pin What is the implication if a design connects a single ended clock to the N-side, in addition to a separate single-ended clock on the P-side. This seems to violate this rule, but what is the implication? |
|
相关推荐
4个回答
|
|
如果单端时钟是输入与输出,这是否重要?
我已经在设计的几个输出上看到了这一点。 试图确定是否存在真正的劣势。 以上来自于谷歌翻译 以下为原文 And does it matter if the single ended clocks are inputs vs. outputs. I've seen this on a few outputs on a design. Trying to determine if there is a true disadvantage. |
|
|
|
“如果设计将单端时钟连接到N端,除了在P端有一个单独的单端时钟之外,这意味着什么。这似乎违反了这个规则,但这意味着什么呢?”
这意味着您将无法使用专用路由将该N侧引脚信号路由到全局缓冲区或时钟管理块(CMT)。 你可以使用CLOCK_DEDICATED_ROUTE约束来解决这个问题,但是你不会以这种方式获得最佳时钟。 “如果单端时钟是输入与输出,这是否重要。” 本用户指南意义上的“时钟”始终是输入。 如果要将时钟转发到另一个芯片(时钟输出),则无需使用专用时钟引脚。 - Gabor 以上来自于谷歌翻译 以下为原文 "What is the implication if a design connects a single ended clock to the N-side, in addition to a separate single-ended clock on the P-side. This seems to violate this rule, but what is the implication?" The implication is that you won't be able to route that N-side pin signal to a global buffer or clock management tile (CMT) using dedicated routing. You could work around this using the CLOCK_DEDICATED_ROUTE constraint, but you won't get an optimal clock that way. "And does it matter if the single ended clocks are inputs vs. outputs." "Clocks" in the sense of this user guide are always inputs. If you want to forward a clock to another chip, (clock output) then there is no need to use a dedicated clock capable pin. -- Gabor |
|
|
|
但是如果将单端时钟输入馈送到BUFR会好吗?
也就是说,连接到N侧的单端时钟 以上来自于谷歌翻译 以下为原文 But it would be OK if the single ended clock input is fed to a BUFR? That is, the single-ended clock that is connected to the N-side |
|
|
|
也就是说,连接到N侧的单端时钟
以上来自于谷歌翻译 以下为原文 That is, the single-ended clock that is connected to the N-side |
|
|
|
只有小组成员才能发言,加入小组>>
2420 浏览 7 评论
2823 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2294 浏览 9 评论
3374 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2461 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
1158浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
584浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
450浏览 1评论
2005浏览 0评论
729浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-12-23 04:58 , Processed in 1.321390 second(s), Total 52, Slave 46 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号